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  Subjects -> AERONAUTICS AND SPACE FLIGHT (Total: 120 journals)
Showing 1 - 30 of 30 Journals sorted alphabetically
Acta Astronautica     Hybrid Journal   (Followers: 484)
Advances in Aerospace Engineering     Open Access   (Followers: 66)
Advances in Aerospace Science and Technology     Open Access   (Followers: 7)
Advances in Astronautics Science and Technology     Hybrid Journal  
Advances in Space Research     Full-text available via subscription   (Followers: 454)
Aeronautical Journal, The     Hybrid Journal   (Followers: 10)
Aerospace     Open Access   (Followers: 57)
Aerospace Medicine and Human Performance     Full-text available via subscription   (Followers: 14)
Aerospace Science and Technology     Hybrid Journal   (Followers: 422)
Aerospace Scientific Journal     Open Access   (Followers: 15)
Aerospace Systems     Hybrid Journal   (Followers: 3)
Aerospace technic and technology     Open Access   (Followers: 2)
Aerotecnica Missili & Spazio : Journal of Aerospace Science, Technologies & Systems     Hybrid Journal  
AIAA Journal     Hybrid Journal   (Followers: 1177)
Air Force Magazine     Full-text available via subscription   (Followers: 11)
Air Medical Journal     Hybrid Journal   (Followers: 8)
Annual of Navigation     Open Access   (Followers: 22)
Artificial Satellites     Open Access   (Followers: 23)
ASTRA Proceedings     Open Access   (Followers: 2)
Astrodynamics     Hybrid Journal   (Followers: 1)
Aviation     Open Access   (Followers: 15)
Aviation Advances & Maintenance     Open Access   (Followers: 3)
Aviation in Focus - Journal of Aeronautical Sciences     Open Access   (Followers: 10)
Aviation Psychology and Applied Human Factors     Hybrid Journal   (Followers: 26)
Aviation Week     Full-text available via subscription   (Followers: 438)
Canadian Aeronautics and Space Journal     Full-text available via subscription   (Followers: 33)
CEAS Aeronautical Journal     Hybrid Journal   (Followers: 29)
Chinese Journal of Aeronautics     Open Access   (Followers: 20)
Ciencia y Poder Aéreo     Open Access   (Followers: 2)
Civil Aviation High Technologies     Open Access   (Followers: 5)
Control Systems     Hybrid Journal   (Followers: 317)
Cosmic Research     Hybrid Journal   (Followers: 4)
COSPAR Colloquia Series     Full-text available via subscription   (Followers: 11)
Egyptian Journal of Remote Sensing and Space Science     Open Access   (Followers: 24)
Elsevier Astrodynamics Series     Full-text available via subscription   (Followers: 12)
Fatigue of Aircraft Structures     Open Access   (Followers: 15)
Frontiers in Astronomy and Space Sciences     Open Access   (Followers: 12)
Gyroscopy and Navigation     Hybrid Journal   (Followers: 255)
IEEE Aerospace and Electronic Systems Magazine     Full-text available via subscription   (Followers: 276)
IEEE Journal on Miniaturization for Air and Space Systems     Hybrid Journal   (Followers: 2)
IEEE Transactions on Aerospace and Electronic Systems     Hybrid Journal   (Followers: 383)
IEEE Transactions on Circuits and Systems I: Regular Papers     Hybrid Journal   (Followers: 39)
International Journal of Aeroacoustics     Hybrid Journal   (Followers: 39)
International Journal of Aerodynamics     Hybrid Journal   (Followers: 36)
International Journal of Aeronautical and Space Sciences     Hybrid Journal   (Followers: 2)
International Journal of Aerospace Engineering     Open Access   (Followers: 80)
International Journal of Aerospace Psychology     Hybrid Journal   (Followers: 23)
International Journal of Aerospace Sciences     Open Access   (Followers: 30)
International Journal of Applied Geospatial Research     Hybrid Journal   (Followers: 7)
International Journal of Aviation Management     Hybrid Journal   (Followers: 8)
International Journal of Aviation Technology, Engineering and Management     Full-text available via subscription   (Followers: 7)
International Journal of Aviation, Aeronautics, and Aerospace     Open Access   (Followers: 4)
International Journal of Crashworthiness     Hybrid Journal   (Followers: 12)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 11)
International Journal of Satellite Communications Policy and Management     Hybrid Journal   (Followers: 13)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 11)
International Journal of Space Structures     Full-text available via subscription   (Followers: 17)
International Journal of Space Technology Management and Innovation     Full-text available via subscription   (Followers: 10)
International Journal of Sustainable Aviation     Hybrid Journal   (Followers: 5)
International Journal of Turbo and Jet-Engines     Hybrid Journal   (Followers: 6)
Investigación Pecuaria     Open Access   (Followers: 3)
Journal of Aerodynamics     Open Access   (Followers: 17)
Journal of Aeronautical Materials     Open Access   (Followers: 9)
Journal of Aeronautics & Aerospace Engineering     Open Access   (Followers: 28)
Journal of Aerospace Engineering     Full-text available via subscription   (Followers: 68)
Journal of Aerospace Engineering & Technology     Full-text available via subscription   (Followers: 16)
Journal of Aerospace Information Systems     Hybrid Journal   (Followers: 20)
Journal of Aerospace Information Systems     Hybrid Journal   (Followers: 32)
Journal of Aerospace Technology and Management     Open Access   (Followers: 7)
Journal of Aircraft     Hybrid Journal   (Followers: 337)
Journal of Aircraft and Spacecraft Technology     Open Access   (Followers: 8)
Journal of Airline and Airport Management     Open Access   (Followers: 12)
Journal of Astrobiology & Outreach     Open Access   (Followers: 3)
Journal of Aviation Technology and Engineering     Open Access   (Followers: 11)
Journal of Aviation/Aerospace Education & Research     Open Access   (Followers: 2)
Journal of Engineering and Technological Sciences     Open Access   (Followers: 1)
Journal of Guidance, Control, and Dynamics     Hybrid Journal   (Followers: 204)
Journal of KONBiN     Open Access   (Followers: 3)
Journal of Navigation     Hybrid Journal   (Followers: 279)
Journal of Propulsion and Power     Hybrid Journal   (Followers: 609)
Journal of Space Safety Engineering     Hybrid Journal   (Followers: 7)
Journal of Space Weather and Space Climate     Open Access   (Followers: 27)
Journal of Spacecraft and Rockets     Hybrid Journal   (Followers: 770)
Journal of Spatial Science     Hybrid Journal   (Followers: 3)
Journal of the American Helicopter Society     Full-text available via subscription   (Followers: 7)
Journal of the Astronautical Sciences     Hybrid Journal   (Followers: 8)
Journal of the Australasian Society of Aerospace Medicine     Open Access   (Followers: 1)
Journal of Wind Engineering and Industrial Aerodynamics     Hybrid Journal   (Followers: 16)
Life Sciences in Space Research     Hybrid Journal   (Followers: 3)
MAD - Magazine of Aviation Development     Open Access   (Followers: 2)
Mekanika : Jurnal Teknik Mesin i     Open Access   (Followers: 1)
Microgravity Science and Technology     Hybrid Journal   (Followers: 2)
New Space     Hybrid Journal   (Followers: 6)
Nonlinear Dynamics     Hybrid Journal   (Followers: 19)
npj Microgravity     Open Access   (Followers: 3)
Open Aerospace Engineering Journal     Open Access   (Followers: 1)
Population Space and Place     Hybrid Journal   (Followers: 9)
Problemy Mechatroniki. Uzbrojenie, lotnictwo, inżynieria bezpieczeństwa / Problems of Mechatronics. Armament, Aviation, Safety Engineering     Open Access   (Followers: 3)
Proceedings of the Human Factors and Ergonomics Society Annual Meeting     Hybrid Journal   (Followers: 16)
Proceedings of the Institution of Mechanical Engineers Part G: Journal of Aerospace Engineering     Hybrid Journal   (Followers: 45)
Progress in Aerospace Sciences     Full-text available via subscription   (Followers: 79)
Propulsion and Power Research     Open Access   (Followers: 67)
REACH - Reviews in Human Space Exploration     Full-text available via subscription   (Followers: 5)
Research & Reviews : Journal of Space Science & Technology     Full-text available via subscription   (Followers: 17)
RocketSTEM     Free   (Followers: 6)
Russian Aeronautics (Iz VUZ)     Hybrid Journal   (Followers: 24)
Science and Education : Scientific Publication of BMSTU     Open Access   (Followers: 1)
Space and Polity     Hybrid Journal   (Followers: 4)
Space Policy     Hybrid Journal   (Followers: 30)
Space Research Today     Full-text available via subscription   (Followers: 48)
Space Safety Magazine     Free   (Followers: 51)
Space Science International     Open Access   (Followers: 193)
Space Science Reviews     Hybrid Journal   (Followers: 97)
SpaceNews     Free   (Followers: 824)
Spatial Information Research     Hybrid Journal   (Followers: 1)
Technical Soaring     Full-text available via subscription   (Followers: 1)
Transport and Aerospace Engineering     Open Access   (Followers: 1)
Transportmetrica A : Transport Science     Hybrid Journal   (Followers: 8)
Unmanned Systems     Hybrid Journal   (Followers: 5)
Вісник Національного Авіаційного Університету     Open Access   (Followers: 2)

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Similar Journals
Journal Cover
IEEE Transactions on Circuits and Systems I: Regular Papers
Journal Prestige (SJR): 0.869
Citation Impact (citeScore): 4
Number of Followers: 39  
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
ISSN (Print) 1057-7122 - ISSN (Online) 1549-8328
Published by IEEE Homepage  [229 journals]
  • IEEE Transactions on Circuits and Systems—I:Regular Papers
           publication information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • IEEE Circuits and Systems Society Information
    • Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based
           on Current Integrating Sampler
    • Pages: 557 - 568
      Abstract: This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter’s front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers’ inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC’s power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Universal Frequency-Domain Analysis of N-Path Networks
    • Pages: 569 - 580
      Abstract: N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband true time delay, providing a path to miniaturization of various reciprocal and nonreciprocal devices. The analytical treatment of these networks, however, remains challenging, because their operation involves frequency mixing produced by the time modulation. In this article, we present a highly accurate frequency-domain approach for the analysis of N-path networks based on perturbation theory. Our method compares favorably to the state-of-the-art polyphase analysis by being much simpler mathematically, yet providing results essentially indistinguishable from numerical simulations, while offering physical insights into the N-path filter operation. We particularize the solution for the high-Q operation regime and obtain simple closed-form analytical expressions for harmonic transfer functions, scattering parameters and baseband impedance.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A High-Temperature Model for GaN-HEMT Transistors and its Application to
           Resistive Mixer Design
    • Pages: 581 - 591
      Abstract: This article presents a high temperature model for gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC). The proposed model for the channel resistance $text {R}_{text {ds}}$ is based on an empirical nonlinear model. The model is applied to design a resistive mixer of a high temperature transceiver for downhole communications through a systematic approach and estimate the performance of the mixer. The proposed model matches well with measurement results of the mixer and accurately estimates its performance at temperatures up to 250 °C. The model is also applied to obtain the optimal gate bias voltage of the mixer for a given temperature. The optimal bias voltage scheme reduces the conversion loss of the mixer by a factor of 8.4 dB at 250 °C under the local oscillator power of −10 dBm.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • An SoC FPAA Based Programmable, Ladder-Filter Based, Linear-Phase Analog
    • Pages: 592 - 602
      Abstract: This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of $2.9mu text{s}$ and $4.2mu text{s}$ for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Fully Synthesizable Fractional-N MDLL With Zero-Order
           Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase
           Offset Calibration
    • Pages: 603 - 616
      Abstract: In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional- ${N}$ multiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional- ${N}$ and integer- ${N}$ modes, respectively. The fractional spur is less than −59.0dBc, and the reference spur is −64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of −240.4dB and −245.5dB.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A 0.11–0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for
           Robust Neurocomputing
    • Pages: 617 - 630
      Abstract: This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 – 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 – 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/I DS
    • Pages: 631 - 640
      Abstract: An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using $mathscr {C} = text {C}/text {I}_{text {DS}}$ as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET) biased at IDS. The proposed $mathscr {C}$ -based methodology is used to study speed versus power trade-offs in both continuous-time (CT) and discrete-time (DT) circuits. Predictive Technology Models (PTMs) have been used to study performance of both MOSFET and FinFET (i.e. FET) devices in different technology nodes. This analysis shows that FinFET transistors exhibit a wider medium-inversion region compared to MOSFET devices, making them more convenient for high-speed and low-power designs. Additionally, this study proves that a lower sub-threshold slope factor results in an improved energy-efficiency of analog circuits.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based
           Background Calibration in 28-nm CMOS
    • Pages: 641 - 654
      Abstract: This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Fractional Order Notch Filter to Compensate the Attenuation-Loss Due to
           Change in Order of the Circuit
    • Pages: 655 - 666
      Abstract: Analog integer order notch filters (IONF) are practically realised by using two or more capacitors. If the dissipation factor of capacitors (used in the IONF) increases then the overall order of the circuit reduces. Reduction in the order causes attenuation-loss at the notch frequency. Once the order reduces, the loss can only be compensated by reducing the quality factor of the IONF circuit, which is not desirable. This problem can be overcome by using a fractional order notch filter (FONF). The FONF circuit uses fractional order capacitors ( $Z=frac {1}{Cs^beta }$ ), which provides an extra degree of design freedom to control the order of the circuit, thereby helping in compensating the attenuation-loss. In this work, a new fractional order notch filter (FONF) has been proposed in which the attenuation-loss, due to change in the order of the system, can be compensated by tuning resistor/s of the proposed circuit.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for
           Processing Neural Networks
    • Pages: 667 - 679
      Abstract: A novel 4T2C ternary embedded DRAM (eDRAM) cell is proposed for computing a vector-matrix multiplication in the memory array. The proposed eDRAM-based compute-in-memory (CIM) architecture addresses a well-known Von Neumann bottle-neck in the traditional computer architecture and improves both latency and energy in processing neural networks. The proposed ternary eDRAM cell takes a smaller area than prior SRAM-based bitcells using 6–12 transistors. Nevertheless, the compact eDRAM cell stores a ternary state (−1, 0, or +1), while the SRAM bitcells can only store a binary state. We also present a method to mitigate the compute accuracy degradation issue due to device mismatches and variations. Besides, we extend the eDRAM cell retention time to $200~mu text{s}$ by adding a custom metal capacitor at the storage node. With the improved retention time, the overall energy consumption of eDRAM macro, including a regular refresh operation, is lower than most of prior SRAM-based CIM macros. A $128times 128$ ternary eDRAM macro computes a vector-matrix multiplication between a vector with 64 binary inputs and a matrix with $64times 128$ ternary weights. Hence, 128 outputs are generated in parallel. Note that both weight and input bit-precisions are programmable for supporting a wide range of edge computing applications with different performance requirements. The bit-precisions are readily tunable by assigning a variable number of eDRAM cells per weight or adding multiple pulses to input. An embedded column ADC based on replica cells sweeps the reference level for $2^{mathrm {N}}-1$ cycles and converts the analog accumulated bit-ine voltage to a 1-5bit digital output. A critical bitline accumulate operation is simulated (Monte-Carlo, 3K runs). It shows the standard deviation of 2.84% that could degrade the classification accuracy of the MNIST dataset by 0.6% and the CIFAR-10 dataset by 1.3% versus a baseline with no variation. The simulated energy is 1.81fJ/operation, and the energy efficiency is 552.5-17.8TOPS/W (for 1-5bit ADC) at 200MHz using 65nm technology.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS
           Current Mode Logic
    • Pages: 680 - 691
      Abstract: In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter,
           Termination Scheme and 12:1 SerDes in 40-nm CMOS
    • Pages: 692 - 703
      Abstract: A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter that reduces the power of the link by 35% with a 0.4-V power supply. The SRAM utilizes an inverted bit insertion scheme that compensates for the degradation of the first transmitted bit, a coil termination scheme that aims to eliminate the ringing of 3D inductive coupling bus, and a 12:1 SerDes that minimizes power consumption and area overhead in inductive coupling channels. Low-power, large-capacity, 3-cycle latency 3D-stacked SRAM for a DNN accelerator is achieved with the combination of these techniques to serve as a replacement of 3D-stacked DRAM. The performance of the proposed 3D-SRAM is compared with HBM DRAM and achieves more than 50% lower energy consumption. The scaling scenario of the SRAM module is discussed in light of the scaling of the inductive coupling technology and logic process.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • RoadNet-RT: High Throughput CNN Architecture and SoC Design for Real-Time
           Road Segmentation
    • Pages: 704 - 714
      Abstract: In recent years, convolutional neural network (CNN) has gained popularity in many engineering applications especially for computer vision. In order to achieve better performance, more complex structures and advanced operations are incorporated into neural networks, which results in very long inference time. For time-critical tasks such as autonomous driving and virtual reality, real-time processing is fundamental. In order to reach real-time processing speed, a lightweight, high-throughput CNN architecture namely RoadNet-RT is proposed for road segmentation in this article. It achieves 92.55% MaxF score on KITTI road segmentation dataset. The inference time is about 9 ms per frame when running on GTX 1080 GPU. Comparing to the state-of-the-art network, RoadNet-RT speeds up the inference time by a factor of 17.8 at the cost of only 3.75% loss in accuracy. What is more, on CamVid dataset its accuracy is 92.98%. Several techniques such as depthwise separable convolution and non-uniformed kernel size convolution are optimized in the hardware accelerator design. The proposed CNN architecture has been successfully implemented on a ZCU102 MPSoC FPGA that achieves the computation capability of 331 GOPS using INT8 quantization. The system throughput reaches 196.7 frames per second with input image size of $280times 960$ . The source code is published at https://github.com/linbaiwpi/RoadNet-RT.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method
           for Computing Nth Roots of Floating-Point Numbers
    • Pages: 715 - 727
      Abstract: State-of-the-art approaches that perform root computations based on the COordinate Rotation Digital Computer (CORDIC) algorithm suffer from high latency in performing multiple iterations. Therefore, root computations based on the CORDIC algorithm cannot meet the strict latency requirements of some applications. In this paper, we propose a methodology for performing ${N}$ th root computations on floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method divides an ${N}$ th root computation into several subtasks approximated by the PWL algorithm. It determines the widest segments of the subtasks and the smallest fractional width needed to satisfy the predefined maximum relative error $Max_{}Err_{r}$ . Our design is coded in Verilog HDL and synthesized under TSMC 40 nm CMOS technology. The synthesized results show that our design can reach the highest frequency of 2.703 GHz with an area consumption of $2608.84~mu ~text{m}^{2}$ and a power consumption of 2.4476 mW. Compared with one state-of-the-art architecture, our design saves 91.60%, 89.84%, and 63.33% of the area, power, and latency @1.89GHz frequency, respectively, while reducing $Max_{}Err_{r}$ by 57.30%. In addition, it saves 94.52%, 92.68%, and 73.17% of the area, power, and delay @1.89GHz frequency, respectively, and reduces $Max_{}Err_{r}$ by 1.65% -hen compared with the other state-of-the-art design.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Neural Synaptic Plasticity-Inspired Computing: A High Computing Efficient
           Deep Convolutional Neural Network Accelerator
    • Pages: 728 - 740
      Abstract: Deep convolutional neural networks (DCNNs) have achieved state-of-the-art performance in classification, natural language processing (NLP), and regression tasks. However, there is still a great gap between DCNNs and the human brain in terms of computation efficiency. Inspired by neural synaptic plasticity and stochastic computing (SC), we propose neural synaptic plasticity-inspired computing (NSPC) to simulate the human brain’s neural network activity for inference tasks with simple logic gates. The multiplication and accumulation (MAC) is transformed by the wire connectivity in NSPC, which only requires bundles of wires and small width adders. To this end, the NSPC imitates the structure of neural synaptic plasticity from a circuit wires connection perspective. Furthermore, from the principle of NSPC, we use a data mapping method to convert the convolution operations to matrix multiplications. Based on the methodology of NSPC, fully-pipelined and low latency architecture is designed. The proposed NSPC accelerator exhibits high hardware efficiency while maintaining a comparable network accuracy level. The NSPC based DCNN accelerator (NSPC-CNN) processes DCNN at $1.5625M$ images/ $s$ with a power dissipation of $15.42~W$ and an area of $36.4~mm^{2}$ . The NSPC based deep neural network (DNN) accelerator (NSPC-DNN) that implements three fully connected layers DNN consumes only $6.6~mm^{2}$ area and $2.93~W$ power, and achieves a throughput of $400M$ -images/ $s$ . Compared with conventional fixed-point implementations, the NSPC-CNN achieves $2.77 times $ area efficiency, $2.25 times $ power efficiency; the proposed NSPC-DNN exhibits $2.31 times $ area efficiency and $2.09 times $ power efficiency.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • High-Throughput Portable True Random Number Generator Based on
           Jitter-Latch Structure
    • Pages: 741 - 750
      Abstract: Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C–80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Hardware-Friendly Approach Towards Sparse Neural Networks Based on
           LFSR-Generated Pseudo-Random Sequences
    • Pages: 751 - 764
      Abstract: The increase in the number of edge devices has led to the emergence of edge computing where the computations are performed on the device. In recent years, deep neural networks (DNNs) have become the state-of-the-art method in a broad range of applications, from image recognition, to cognitive tasks to control. However, neural network models are typically large and computationally expensive and therefore not deployable on power and memory constrained edge devices. Sparsification techniques have been proposed to reduce the memory foot-print of neural network models. However, they typically lead to substantial hardware and memory overhead. In this article, we propose a hardware-aware pruning method using linear feedback shift register (LFSRs) to generate the locations of non-zero weights in real-time during inference. We call this LFSR-generated pseudo-random sequence based sparsity (LGPS) technique. We explore two different architectures for our hardware-friendly LGPS technique, based on (1) row/column indexing with LFSRs and (2) column-wise indexing with nested LFSRs, respectively. Using the proposed method, we present a total saving of energy and area up to 37.47% and 49.93% respectively and speed up of $1.53times $ w.r.t the baseline pruning method, for the VGG-16 network on down-sampled ImageNet.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Continuous-Time, Configurable Analog Linear System Solutions With
           Transconductance Amplifiers
    • Pages: 765 - 775
      Abstract: This paper addresses and experimentally demonstrates a programmable linear equation solver by analog computation. A set of differential equations using transconductance devices directly translated from circuit theory converges to the linear equation solution. These energy-efficient analog techniques are experimentally demonstrated in a configurable analog platform. The resulting analog linear equation solution circuits are effectively analog filters. The paper analyzes the algorithmic issues and analog numerical analysis issues, including accuracy, convergence time, and the interpretation of condition number for analog solutions.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Data-Driven Resilient Control for Linear Discrete-Time Multi-Agent
           Networks Under Unconfined Cyber-Attacks
    • Pages: 776 - 785
      Abstract: In this paper, the resilient control for linear discrete-time multi-agent networks subjected to unconfined cyber-attacks is investigated based on a data-driven method. Firstly, according to the evolution of the original network dynamics, a distributed data-driven estimation algorithm is presented. On this basis, a switching control law is proposed to solve the resilient consensus problem for the discrete-time multi-agent network under unconfined cyber-attacks. Further, some necessary and sufficient conditions for designing the resilient controllers are obtained by solving a nonlinear matrix inequation. Secondly, the proposed data-driven method is extended to study the resilient tracking control and formation control problems. Finally, some numerical simulations are provided to verify the effectiveness of the data-driven resilient control method.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Adaptive Event-Triggered SMC for Stochastic Switching Systems With
           Semi-Markov Process and Application to Boost Converter Circuit Model
    • Pages: 786 - 796
      Abstract: In this article, the sliding mode control (SMC) design is studied for a class of stochastic switching systems subject to semi-Markov process via an adaptive event-triggered mechanism. Network-induced communication constraints, semi-Markov switching parameters, and uncertain parameters are considered in a unified framework for the SMC design. Due to the constraint of measuring transducers, the system states always appear with unmeasurable characteristic. Compared with the traditional event-triggered mechanism, the adaptive event-triggered mechanism can effectively reduce the number of triggering than the static event-triggered mechanism. During the data transmission of network communication systems, network-induced delays are characterized from the event trigger to the zero-order holder. The aim of this work is to design an appropriate SMC law based on an adaptive event-triggered communication scheme such that the resulting closed-loop system could realize stochastic stability and reduce communication burden. By introducing the stochastic semi-Markov Lyapunov functional, sojourn-time-dependent sufficient conditions are established for stochastic stability. Then, a suitable SMC law is designed such that the system state can be driven onto the specified sliding surface in a finite-time region. Finally, the simulation study on boost converter circuit model (BCCM) illustrates the effectiveness of the theoretical findings.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Event-Triggered Sliding Mode Control of Power Systems With Communication
           Delay and Sensor Faults
    • Pages: 797 - 807
      Abstract: As large-scale power systems are more and more closely integrated with remote transmission technologies, they are also affected by malicious factors in the cyber and physical layers when bringing convenience. In this article, we propose a novel adaptive event-triggered strategy and apply to the multi-area power system to deal with the load frequency control (LFC) problem with network-induced delay and stochastic sensor faults based on the discrete-time sliding mode control (DSMC) technique. Compared with existing event-triggered strategies, the proposed event-triggered strategy dynamically adjusts the threshold according to system state fluctuations, which can improve the system’s tolerance for sensor faults and reduce the number of transmitted packets. Firstly, a dynamic LFC model combining network-induced delay, sensor faults, adaptive event-triggered strategy and DSMC is proposed by using the analysis method of time-delay system. Then we devise an appropriate discrete-time sliding surface for each subsystem in the networked power systems. The Lyapunov stability theory is used to analyze the asymptotic stability and robustness of each subsystem, and the decentralized controller design method is derived. Finally, some simulation examples are introduced to confirm the effectiveness of the proposed adaptive event-triggered DSMC approach.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Dynamic Event-Triggered Tracking Control for a Class of
           p-Normal Nonlinear Systems
    • Pages: 808 - 817
      Abstract: This paper investigates the problem of dynamic event-triggered output feedback tracking control for a class of $p$ -normal nonlinear systems with unknown growth rate. To cope with the unknown growth rate imposed on the system nonlinearities, a dynamic gain technique is introduced and a constructive coordinate transformation is given. On the other hand, an event-triggered strategy combining with the dynamic gain is proposed such that the triggering threshold can be adjusted in an adaptive manner. With the help of the proposed event-triggered strategy, a dynamic event-based output feedback controller is developed to ensure that all signals of the closed-loop system are bounded while the tracking error converges to a small neighborhood of the origin. Moreover, it is proved that the Zeno behavior is excluded in the presence of nonsmooth controller. Two examples, including an induction heater circuit system and a numerical example, are provided to indicate the effectiveness of the proposed control method.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • H∞ Stabilization of Discrete-Time Nonlinear Semi-Markov Jump Singularly
           Perturbed Systems With Partially Known Semi-Markov Kernel Information
    • Pages: 818 - 828
      Abstract: In this paper, the $mathcal {H}_{infty }$ stabilization problem is studied for discrete-time semi-Markov jump singularly perturbed systems (SMJSPSs) with repeated scalar nonlinearities. As the exact statistical information of the sojourn time or the mode transition is difficult to obtain, the case with only partial semi-Markov kernel information available is considered. Furthermore, introducing an external disturbance or nonlinearity into the analysis of discrete-time semi-Markov jump systems (DTSMJSs) meets critical obstacles, since the relation between the system state vectors at two nonadjacent instants is difficult to determine. To address this issue, the variation trend of the Lyapunov function for a semi-Markov jump sequence is analyzed in detail. Subsequently, criteria of mean-square exponential stability (MSES) for DTSMJSs are established for the first time based on the Lyapunov stability theory. By virtue of the criteria obtained and the cone complementary linearization algorithm, a controller ensuring MSES and $mathcal {H}_{infty }$ performance for discrete-time nonlinear SMJSPSs is constructed. Finally, the effectiveness and applicability of the proposed method are validated by simulation examples including an inverted pendulum model.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Distributed Adaptive Finite-Time Compensation Control for UAV Swarm With
           Uncertain Disturbances
    • Pages: 829 - 841
      Abstract: Aimed at the problem that the unmanned aerial vehicle (UAV) close formation cannot maintain its desired formation shape due to the wind field disturbances, a novel distributed adaptive control approach is proposed to counteract the lateral and forward distance errors caused by uncertain wind field disturbances. Firstly, based on the “leader-follower” model, an adaptive control law is designed to accurately estimate the magnitude and direction of the wind in 3-D space. Then, the distance errors caused by uncertain wind field disturbances is counteracted by controlling UAV relative movement. Moreover, their velocity can keep constant to achieve the desired formation shape. Additionally, the signals of the closed-loop system are semi-globally practical finite-time stable (SGPFS). Finally, the simulation results show that the proposed adaptive control algorithm has good robustness, which provides a theoretical basis for engineering practice.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Time Domain Solution Analysis and Novel Admissibility Conditions of
           Singular Fractional-Order Systems
    • Pages: 842 - 855
      Abstract: This paper investigates the regularity, non-impulsiveness, stability and admissibility of the singular fractional-order systems with the fractional-order $alpha in (0,1)$ . Firstly, the structure, existence and uniqueness of the time domain solutions of singular fractional-order systems are analyzed based on the Kronecker equivalent standard form. The necessary and sufficient condition for the regularity of singular fractional-order systems is proposed on the basis of the above analysis. Secondly, the necessary and sufficient conditions of non-impulsiveness as well as stability are obtained based on the proposed time domain solutions of singular fractional-order systems, respectively. Thirdly, two novel sufficient and necessary conditions for the admissibility of singular fractional-order systems are derived including the non-strict linear matrix inequality form and the linear matrix inequality form with equality constraints. Finally, two numerical examples are given to show the effectiveness of the proposed results.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Dynamic Event-Based Non-Fragile Dissipative State Estimation for Quantized
           Complex Networks With Fading Measurements and Its Application
    • Pages: 856 - 867
      Abstract: This article is concerned with the issue of dynamic event-based non-fragile dissipative state estimation for a type of stochastic complex networks (CNs) subject to a randomly varying coupling as well as fading measurements, where the variation of coupling is governed by a Markov chain. To characterize the measurement fading phenomenon for different nodes, a Rice fading model is considered with known statistics information of the coefficients. For the sake of further resource saving, a dynamic event-triggering strategy (ETS), which is proved to release less data packets than the static one, is implemented to govern the measurements transmission for each sensor to its corresponding estimator. The main objective of this article is to determine a dynamic event-based non-fragile estimator such that, for all possible parameter fluctuations in estimator gains, the estimation error system is stochastically stable with a strict ( $Upsilon _{1}, Upsilon _{2}, Upsilon _{3}$ )- $gamma $ -dissipativity. Through intensive stochastic analysis, sufficient conditions are then derived in terms LMI to guarantee the existence of the desired state estimator. Finally, the effectiveness of the proposed results are verified by two practical examples of Chua’s circuit and quadruple-tank process system (QTPS).
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • CMOS Full-Duplex Mixer-First Receiver With Adaptive Self-Interference
    • Pages: 868 - 878
      Abstract: A full-duplex transceiver with on-chip self-inter-ference-cancellation (SIC) is presented. The achieved SIC is 110 dB, and it is realized in three stages: RF front-end hybrid, baseband analog, and baseband digital. An integrated hybrid is used in the RF front-end which employs an adaptive tuning impedance network (TIN) to track the antenna impedance variations, achieving over 50 dB of SIC. $N$ -path mixer-first architecture is used for the receiver to improve the linearity and to provide out of band blocker cancellation. The self-interference is further attenuated in the analog domain using the down-converted sample of the transmit signal. The analog transmit interference canceler (TIC) receives the sampled copy of the transmitted signal of the power amplifier and offers adaptive amplitude and phase adjustment for the cancellation signal, obtaining more than 20 dB on-chip cancellation in the analog domain. The last step of SIC is realized in the digital domain using a nonlinear system with memory to cancel the remnant of self-interference and distortions, resulting in 43 dB of SIC. The front-end hybrid, mixer-first receiver, and analog TIC are implemented in a CMOS 65-nm technology. Thanks to adaptive gradient decent algorithm employed in the system, the total SIC of the hybrid and TIC is more than 70 dB, which is one of the highest cancellation values achieved on the chip. The die area is 4 mm2, and the fabricated chip consumes 80 mW dc power. The average transmit power is 23 dBm, and the noise figure of the receiver in the full-duplex mode is 11 dB.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes
    • Pages: 879 - 891
      Abstract: Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Reconfigurable Passive Mixer-Based Sub-GHz Receiver Front-End for Fast
           Spectrum Sensing Functionality
    • Pages: 892 - 903
      Abstract: A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves −22.3 dBm out-of-band IIP3, and an average 3rd LO HRR of 43 dB over 300–800 MHz in DBM&HR mode. Over 600–1200 MHz in SHM mode, it shows >31.8 dB conversion gain, −30.9 dBm in-band IIP3, and > −20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Fixed-Complexity Tree Search Schemes for Detecting Generalized Spatially
           Modulated Signals: Algorithms and Hardware Architectures
    • Pages: 904 - 917
      Abstract: In the generalized spatial modulation (GenSM) multiple input multiple output (MIMO) system, each block of data bits is mapped to a set of spatially multiplexed (SMX) symbols and an index of transmit antenna combination (TAC) of active antennas. The difficulty for the GenSM MIMO receiver is to detect the SMX symbols and TAC index simultaneously. Recently, we applied the conventional sphere decoding algorithm (SDA) successively to achieve the exact maximum likelihood detection (MLD) of GenSM MIMO signals. The SDA scheme suffers from variable computational complexity and leads to hardware detectors with variable throughput rate. Instead, fixed-complexity tree search algorithms, e.g., reduced fixed sphere decoding (rFSD), with nearly MLD performance are employed to facilitate hardware implementation. Here, we propose to apply the rFSD successively and design a hardware architecture for detecting GenSM MIMO signals under the scenario of 5 transmit antennas, 2 transmit radio frequency chains, 4 receive antennas, and 64-QAM SMX symbols. The VLSI implementation results under the TSMC 90nm CMOS technology reveal that our architecture requires 276.7K gates and provides detection throughput 1.613 Gbps, while operating at 322.6 MHz. Compared with other related architectures, our architecture provides higher detection throughput rate and is of better hardware efficiency.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Distributed Control of Multi-Functional Grid-Tied Inverters for Power
           Quality Improvement
    • Pages: 918 - 928
      Abstract: Multi-functional grid-tied inverters (MFGTIs) have been investigated recently for improving the power quality (PQ) of microgrids (MGs) by exploiting the residual capacity (RC) of distributed generators. Several centralized and decentralized methods have been proposed to coordinate the MFGTIs. However, with the increasing number of the MFGTIs, it demands a method with improved reliability and flexibility, which are characteristics of distributed framework that has not been introduced into the PQ improvement (PQI) field before. In this paper, we propose a distributed consensus method to undertake the PQI task. The task is proportionally shared among the MFGTIs according to their instant RCs. Besides, most of the existing methods assume that the RCs of the MFGTIs are sufficient for tackling the PQ problem (PQP), which is not always true. In the case of insufficient RC, the active power output of each MFGTI is scaled down by the same factor determined by a proposed leader-follower protocol to make room for the task. In summary, the PQP is dealt with in both cases of sufficient and insufficient RC under the distributed control framework. Finally, simulations and hardware-in-the-loop experiments of an MG consisting of three 10kVA MFGTIs are presented to verify the effectiveness of the proposed methods.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Frequency Splitting Elimination and Utilization in Magnetic Coupling
           Wireless Power Transfer Systems
    • Pages: 929 - 939
      Abstract: A design methodology for making magnetic coupling wireless power transfer (MC-WPT) systems resonate at given frequencies is proposed in this paper. Proposing such a method not only can improve the energy efficiency against frequency splitting, but also can satisfy the requirement of frequency standards and then promote its industrial application. The method is based on eigenvalues configuration and comprehensively considers all electric parameters. The quantitative relationship between the performance indexes and electric parameters is derived, based on which the expected electric parameters can be quickly and accurately determined. The design theory and design flow are provided, and practical systems are designed, simulated and measured to show the effectiveness of the proposed method. The results show that the proposed method can: 1) eliminate frequency splitting to make MC-WPT systems resonate at a given frequency; 2) utilize frequency splitting to make MC-WPT systems resonate at two given frequencies.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Rapid Circle Centre-Line Concept-Based MPPT Algorithm for Solar
           Photovoltaic Energy Conversion Systems
    • Pages: 940 - 949
      Abstract: The perturb & observe (P&O) algorithm is very popular for maximum power point tracking (MPPT) for solar photovoltaic (PV) systems. However, it has tracking problems during varying irradiations as well as the nuisance of oscillations around the maximum power point (MPP). This work introduces a circle center-line concept based P&O (CCCP&O) algorithm for MPPT, where, the concept of circle and its center are combined with the P&O algorithm. This algorithm tends to reduce the number of iterations taken to reach the MPP, which reduces settling time. Moreover, the problem of large oscillations around the MPP is eliminated by using the concept of flexible step size. The algorithm initializes with standard P&O, but utilizes a approach of diameter equivalence of a circle as a procedure to reach next operating point on the power-voltage plot. Therefore, the iterations required to get to the MPP are reduced substantially. The MPP changes with change in solar irradiance, therefore, a concept of artificial envelope around the P-V curve is used to improve tracking of the algorithm during varying irradiances. The overall performance of the algorithm is demonstrated and compared in simulation using SIMULINK MATLAB as well as also shown experimentally in a developed hardware prototype.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • A Novel Digital Control Method of Primary-Side Regulated Flyback With
           Active Clamping Technique
    • Pages: 950 - 962
      Abstract: Because of the different working principles between conventional flyback and active-clamped flyback (ACF), the existing primary-side regulation (PSR) technology cannot be applied to ACF. And in order to achieve PSR of ACF, a low-cost digital sampling method based on the auxiliary winding of the transformer is proposed. In the conventional peak current mode (PCM) controlled ACF, the sampling resistor of primary current may introduce additional power loss, and high-frequency oscillations during sampling may reduce system’s stability. Therefore, a digital feedback-feedforward control (FFC) method is proposed to eliminate the sampling resistor. The stability of the proposed control method and its influence on the dynamic response are studied. In addition, since GaN device has higher power loss during reverse conduction than its Si counterpart, design considerations of reverse conduction time of power switches are also discussed in this paper. All control methods and design considerations are verified on a GaN-based 12V-3A ACF, and the proposed control strategy is implemented by FPGA.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • IEEE Transactions on Circuits and Systems—I:Regular Papers
           information for authors
    • Pages: 963 - 963
      Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
  • Special Issue for 50 th B irthday of Memristor:
    • Pages: 964 - 964
      Abstract: Presents the front cover for this issue of the publication.
      PubDate: Feb. 2021
      Issue No: Vol. 68, No. 2 (2021)
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