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ISSN (Print) 1943-0663
Published by Institute of Electrical and Electronics Engineers (IEEE)

[164 journals]

[Blank page - back cover]
- Pages: C4 - C4
  Abstract: This page or pages intentionally left blank.
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)
IEEE Embedded Systems Letters information for authors
- Pages: C3 - C3
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)
Table of Contents
- Pages: C1 - C1
  Abstract: Presents the table of contents for this issue of the periodical.
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)
IEEE Embedded Systems Letters publication information
- Pages: C2 - C2
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)
Reliability Guarantees in Automata-Based Scheduling for Embedded Control Software
- Authors: Prabhu M; S.;Hazra, A.;Dasgupta, P.;
  Pages: 17 - 20
  Abstract: Automata-based scheduling is a recent technique for online scheduling of software control components in embedded systems. This letter studies one important aspect of automata-based scheduling that has not been studied in the past, namely resilience to faults. The goal of the proposed technique is to create an automaton that recommends the scheduling patterns that are admissible with respect to control performance requirements, when the state of the system has been mutated by faults. The problem has been formulated as a game between the scheduler and the (possibly faulty) system, where a winning strategy of the scheduler prevents the system from reaching bad states forever. We present a method for analyzing the structure of the game and extracting an automaton that captures the winning strategies of the scheduler, namely the automaton to be used for automata-based scheduling.
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)
High-Speed Hardware Arbitration Supporting Priorities and Bounded Service Latency
- Authors: Kornaros; G.;
  Pages: 21 - 24
  Abstract: Effective utilization of the available resources in network processors and in modern embedded multicore systems primarily requires advanced hardware-based scheduling techniques to manage increasing arbitration rates. In this scope, this letter presents the architecture and a low-cost ultra high-speed implementation of a novel arbiter. While average response time or service throughput is often an inadequate metric when dealing with strict time constraints, the proposed hardware scheme features an innovative scheduling technique supporting prioritization, while at the same time this arbiter guarantees bounded service latency. Based on a dual priority enforcer scheme, a 64-input scheduler is implemented in a standard 0.13 um CMOS technology making approximately over 200 million scheduling decisions per second.
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)
Expanding Gate Level Information Flow Tracking for Multilevel Security
- Authors: Hu; W.;Oberg, J.;Barrientos, J.;Mu, D.;Kastner, R.;
  Pages: 25 - 28
  Abstract: Embedded systems found in critical infrastructures require tight information flow controls to prevent unintended interference between different system components. These critical systems require extensive testing and verification to ensure strict enforcement of information flow policy. To assist in this process, gate level information flow tracking (GLIFT) has been proposed to expose all flows of information through Boolean gates. However, the current work in this realm only considers a two-level security lattice ( ${tt LOW} sqsubset {tt HIGH}$ ). In this letter, we expand the GLIFT method to multilevel security lattices and provide an analysis of the overheads using IWLS benchmarks. Results show that expanding GLIFT to multilevel security lattices produces overheads and we discuss potential research on its applications.
  PubDate: June 2013
  Issue No: Vol. 5, No. 2 (2013)

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