for Journals by Title or ISSN for Articles by Keywords help
 Subjects -> COMPUTER SCIENCE (Total: 2122 journals)     - ANIMATION AND SIMULATION (31 journals)    - ARTIFICIAL INTELLIGENCE (105 journals)    - AUTOMATION AND ROBOTICS (105 journals)    - CLOUD COMPUTING AND NETWORKS (67 journals)    - COMPUTER ARCHITECTURE (10 journals)    - COMPUTER ENGINEERING (11 journals)    - COMPUTER GAMES (21 journals)    - COMPUTER PROGRAMMING (26 journals)    - COMPUTER SCIENCE (1231 journals)    - COMPUTER SECURITY (50 journals)    - DATA BASE MANAGEMENT (14 journals)    - DATA MINING (38 journals)    - E-BUSINESS (22 journals)    - E-LEARNING (30 journals)    - ELECTRONIC DATA PROCESSING (22 journals)    - IMAGE AND VIDEO PROCESSING (40 journals)    - INFORMATION SYSTEMS (107 journals)    - INTERNET (96 journals)    - SOCIAL WEB (53 journals)    - SOFTWARE (34 journals)    - THEORY OF COMPUTING (9 journals) COMPUTER SCIENCE (1231 journals)                  1 2 3 4 5 6 7 | Last
 Analog Integrated Circuits and Signal ProcessingJournal Prestige (SJR): 0.211 Citation Impact (citeScore): 1Number of Followers: 7      Hybrid journal (It can contain Open Access articles) ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030 Published by Springer-Verlag  [2352 journals]
• An enhanced fast-settling recycling folded cascode Op-Amp with improved DC
gain in 90 nm CMOS process
Pages: 243 - 256
Abstract: Proposed in this paper is design and analysis of an enhanced recycling folded cascode (RFC) Op-Amp. This structure is achieved using connecting two nodes and eliminating some devices in the conventional RFC. This effect enhances the DC gain with increasing output resistance of differential pair compared to the conventional RFC circuit. In the same − 3 dB frequency, the unity gain bandwidth is also increased. Moreover, for the same slew rate and input referred noise performance, other proposed improvements are the fast-settling time and total harmonic distortion. Hspice simulation results in 90 nm CMOS standard technology demonstrate that the proposed amplifier has 1.2 times the unity gain bandwidth (190 vs. 160 MHz) and also has twice gain boosting (66.2 vs. 59.5 dB) in the same − 3 dB frequency, power supply (1.2 V) and driving capacitor load of 5 pF.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1273-7
Issue No: Vol. 98, No. 2 (2019)

• Oscillating quiescent point in power amplifier biasing
• Authors: Sunil M. Mutha; B. S. Umre
Pages: 265 - 276
Abstract: Biasing is an essential feature of any electronic circuit. The traditional method of biasing involves applying a proper DC to fix the operating point and thereafter ensure its stability. In this paper, we have proposed a new concept of transistor biasing. Instead of a fixed quiescent point which is normally established by giving DC input to the transistor for the purpose of biasing, we have proposed an oscillating quiescent point by giving square wave biasing input, so that the quiescent point would be oscillating between the two ends of the load line. During the positive half cycle of the input signal the quiescent point would be at the bottom of the load line near the cutoff region, while during negative half cycle of the input signal, the quiescent point would be at the top of the load line near the saturation region, thereby giving full cycle operation for the signal excursion in the active region. The linear range of amplification is better exploited to give higher amplification with negligible distortion and high efficiency.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1293-3
Issue No: Vol. 98, No. 2 (2019)

• Analysis of subthreshold SOI FinFET based two stage OTA for low power
• Authors: Reena Sonkusare; Prathamesh Milind Pilankar; Surendra S. Rathod
Pages: 277 - 289
Abstract: In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by $$g_{m}/I_{D}$$ methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and $$\pm 0.5 V$$ ;respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1305-3
Issue No: Vol. 98, No. 2 (2019)

• A wideband current amplifier with DC-offset cancellation utilizing chopper
modulation
• Authors: Horng-Yuan Shih; Yu-Chuan Chang; Cheng-Wei Yang
Pages: 291 - 297
Abstract: A wideband current amplifier with DC-offset cancellation utilizing chopper modulation is proposed. Combining series–series feedback with backgate driven choppers, a wideband current amplifier with DC-offset cancellation is realized. As consumed a power of 1.495 mW under a supply voltage of 1.8 V, measured bandwidth of the current amplifier is 120 MHz, which leads the current amplifier can be adopted to compose the analog baseband of a wideband direct-conversion receiver with bandwidth of 240 MHz (twice of the baseband bandwidth). Measured current gain of the current amplifier is 15 dB. Measured output DC-offset without and with DC-offset cancellation are − 70.8 dBV and − 91 dBV, respectively. Thus, DC-offset reduction of 20 dB is achieved.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1376-1
Issue No: Vol. 98, No. 2 (2019)

• Design and simulation of all-optical precoder for differential quadrature
phase shift keying (DQPSK) modulator
• Authors: R. Manohari; Shanthi Prince; Satyasai Sribhashyam
Pages: 299 - 310
Abstract: Differential quadrature phase shift keying (DQPSK) encodes the phase change from one symbol period to the next. The precoder is designed for this purpose. The main objective of this paper is to design a simple precoder of the DQPSK transmitter. The precoder is designed using various blocks such as multiplexers, logic gates and flip-flops. The blocks are designed using Mach–Zehnder Interferometer-Semiconductor Optical Amplifier. The designed optical precoder is simulated and tested. It is capable of mapping input bit streams to quadrature components at a data rate up to 10 Gbps. Performance parameters such as Q factor and BER are analyzed for various data rates from 2 to 10 Gbps. The values of Q factor and BER at a data rate of 10 Gbps are found to be 5.4 and 1.5e−8 respectively. Hence, it is suitable for the high-speed transmission system.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1274-6
Issue No: Vol. 98, No. 2 (2019)

• A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell
with expanded read/write stabilities for internet-of-things applications
• Authors: Vishal Sharma; Maisagalla Gopal; Pooran Singh; Santosh Kumar Vishvakarma; Shailesh Singh Chouhan
Pages: 331 - 346
Abstract: With the increased requirement of on-chip data computations in internet of things based applications, the embedded on-chip SRAM memory has been under its renovation stage to overcome the classical problems like stability and poor energy efficiency. In this work, a data-dependent-power-supply mechanism for a new 11T SRAM cell is proposed with ultra-low leakage and improved read/write stability against the process–voltage–temperature variations. The proposed cell consumes static power in the fraction of picowatt range and has considerable enhancement in the value of write static noise margin (WSNM). In addition, the use of associated read decoupling approach, with the column-based read buffer, further improves the read stability of the proposed cell and make it comparable with the hold stability value. The percentage reduction in the leakage power of proposed 11T cell is $$99.97\%$$ , $$99.93\%$$ and $$99.97\%$$ , while the WSNM 1 is $$6.98\times$$ , $$3.12\times$$ and $$1.46\times$$ , and WSNM 0 is $$5.55\times$$ , $$1.25\times$$ and $$1.16\times$$ larger when operating at 0.4 V and compared to the conventional 6T and threshold voltage techniques based VTH_9T and data aware write assist (DAWA) 12T SRAM cell structures respectively. $$I_{read}{/}I_{leak}$$ ratio for the proposed cell has improved by $$6.55\times$$ , $$6.22\times$$ and $$5.11\times$$ when compared with the 6T, VTH_9T and DAWA12T SRAM to increase the memory density. Further, the post-layout Monte Carlo simulation results (2000 samples) confirm the robustness of the proposed cell against the process variations.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1286-2
Issue No: Vol. 98, No. 2 (2019)

• High performance 9T adiabatic SRAM and novel stability characterization
using pole zero placement
• Authors: Sunil Jadav; Rajeevan Chandel
Pages: 347 - 355
Abstract: Stability of memory cells always considered as a most significant figure for defining the logic data at output terminals. And the value of logic data is influenced due to the dominance of leakage component at deep submicron technology. Stability analysis and leakage issues of new 9T adiabatic static random access memory (SRAM) cells is presented using the technique of pole zero concept. With the help of flow graph characteristic of memory cell is modeled and validated using MATLAB tool. The elementary cell of proposed SRAM resembles behavior of 4T-SRAM consisting of two high load resistors constructed of PMOS and cross-coupled NMOS pair. NMOS switch is used to restrict short circuit current and two gradually rising and falling wave pulses with controlled switching current flow. The simulation is carried out at 180 nm technology and it has been found that the average power dissipation of the proposed SRAM reduces by a factor of 41 with no performance degradation and energy is efficiently recovered using adiabatic and body biasing technique.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1308-0
Issue No: Vol. 98, No. 2 (2019)

• Miniaturized microstrip dual-band bandpass filter with wide upper
stop-band bandwidth
• Authors: Shiva Khani; Mohammad Danaie; Pejman Rezaei
Pages: 367 - 376
Abstract: A novel microstrip dual-band bandpass filter (BPF) with bended microstrip lines, rectangular resonators and stepped impedance resonator (SIR) is designed, analyzed and fabricated. This circuit provides two pass-bands with the center frequencies of 3.6 and 5.7 GHz. Moreover, the LC equivalent circuits of the basic and main resonators are meticulously computed so as to present an analytical description. The surface current distributions of the proposed filter are shown to verify the performance of the filter and provide physical insight. The measured data of the proposed filter indicate that the insertion losses are better than 0.53 and 0.67 dB and the return losses are 25 and 24.7 dB in the first and second bands, respectively. One of the most outstanding features of the proposed filter is that the upper band can be tuned between 5.7 and 8.4 GHz without any increment in the circuit size. The compact size, wide upper stop-band bandwidth, low insertion loss, sharp transition bands, and high attenuation level in the stop-bands are the other marked positive points of the designed filter. Finally, a suitable agreement between the simulated and measured S-parameters can be observed.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1254-x
Issue No: Vol. 98, No. 2 (2019)

• Novel microstrip branch-line coupler with low phase shift for WLANs
• Authors: A. Rezaei; L. Noori; S. M. Hosseini
Pages: 377 - 383
Abstract: In this work, a novel branch-line coupler is presented using a new type of microstrip cells. The proposed structure is consisting of high and low impedance sections and a main small square closed loops. It operates at 2.4 GHz for WLAN applications. Using the introduced structure, a good passband performance is achieved. An excellent phase balance closed to ideal is obtained with a phase difference of 270 ± 0.037° between output ports. Furthermore, there are low return loss and high isolation better than − 29 and − 30 dB respectively. Meanwhile, the designed coupler has a good insertion loss and coupling factor. Despite of having a high performance, this coupler is relatively compact with an overall size of 0.037 λg2. The designing method is based on proposing an LC model of a basic microstrip cell and finding the effective parameters to obtain a high performance. In order to validate the designing method and simulation results, the presented coupler is fabricated and measured. There is a good agreement between the simulated and measured results.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1255-9
Issue No: Vol. 98, No. 2 (2019)

• Evaluation of a mushroom shape CPW-fed antenna with triple band-notched
characteristics for UWB applications based on multiple attribute decision
making
• Authors: Yashar Zehforoosh
Pages: 385 - 393
Abstract: A CPW-fed ultra-wideband (UWB) planar monopole antenna with triple band-notched characteristics is presented in this paper. In addition, a prototype of the antenna was fabricated and its performance is approved experimentally. Three notched frequency bands are achieved by using a novel inverted V-shaped impedance resonator, two L-shaped open circuit stubs, and T-shaped tuning stub, three band-notched frequencies could be obtained in the WiMAX (3.3–3.6 GHz), WLAN (5.15–5.85 GHz), downlink of X-band satellite communication (7.25–7.75 GHz). Simulated and measurement results show that proposed antenna could perform 2.9–11 GHz (116%), defined by VSWR < 2. The proposed antenna has small size (20 × 20 × 1.6 mm3) with omnidirectional radiation pattern. Also, an evaluation is done based on analytical hierarchy process method for comparison the proposed monopole antenna with some previously presented UWB monopole antennas.
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1292-4
Issue No: Vol. 98, No. 2 (2019)

• A modified Wilkinson power divider with ultra harmonic suppression using
open stubs and lowpass filters
• Authors: Saeed Roshani; Sobhan Roshani; Arash Zarinitabar
Pages: 395 - 399
Abstract: In this paper, a modified 1 GHz Wilkinson power divider with ultra harmonics suppression is proposed. In the presented divider, three open stubs are used at three ports of divider and two compact low-pass filters are used as quarter-wavelength transmission lines paths. The proposed divider shows excellent specifications and suppresses significant number of unwanted harmonics (2nd–30th) with high attenuation, which features the ultra wide stopband bandwidth. To the best knowledge of the authors, the proposed divider shows the widest harmonics rejections band, compared to recent power dividers. The achieved size of the fabricated divider is only 34.6 mm × 31.2 mm (0.14 λg × 0.13 λg).
PubDate: 2019-02-01
DOI: 10.1007/s10470-018-1299-x
Issue No: Vol. 98, No. 2 (2019)

• NanoCMOS optimized DVCC-based quadrature voltage controlled oscillator
performances prediction through bisquare-weights method
• Authors: Houda Daoud; Samir Bensalem; Sawssan Lahiani; Chayma Bensalem; Mourad Loulou
Abstract: This paper dealt with the prediction of optimized quadrature voltage controlled oscillator (QVCO) performances for the upcoming CMOS nanoprocess using the robust bisquare weights (BW) method. Using differential voltage current conveyor, the QVCO was optimized for low power consumption with TSMC 0.18 µm CMOS process under ± 0.9 V supply voltage and relying on the Heuristic method. To provide solutions to the nanoscale CMOS challenges, a synoptic of nanoCMOS circuit performances prediction including the BW method was proposed to predict the performances of the optimized QVCO circuit. Some predicted performances for 45–22 nm process nodes were obtained in order to solve design challenges generated by upcoming analog high frequency (HF) systems with severe requirements. The behaviour of the optimized QVCO performances with process scaling were detailed.
PubDate: 2019-02-14
DOI: 10.1007/s10470-019-01414-0

• An event detection module with a low-power, small-size CMOS image sensor
with reference scaling
• Authors: Cheonwi Park; Woo-Tae Kim; In-June Yeo; Moongu Jeon; Byung-geun Lee
Abstract: This paper presents a low-power and small-size CMOS image sensor (CIS) which can be utilized as a power-efficient event detection system. Since high-resolution images are not required for most event detection purposes, power consumption and chip size of the CIS are optimized only for detection performance. The proposed reference voltage scaling with a multiple input sampling scheme allows the CIS to further minimize power consumption by removing a variable gain amplifier, which is commonly placed in a pixel readout channel. The CIS chip employing a 10 μm-pitch 3T active pixel occupies a die area of 0.98 mm × 0.84 mm. The CIS dissipates 181 μW from 3.0 V analog and 1.4 V digital supplies at the maximum frame rate of 252 fps.
PubDate: 2019-02-13
DOI: 10.1007/s10470-019-01421-1

• A 0.8 μV RMS 8-channel front-end for EEG recording
• Authors: Guocheng Huang; Tao Yin; Haigang Yang; Xinxia Cai
Abstract: A CMOS low-power 8-channel electro-encephalograph front-end circuit is presented. The single-stage instrumental amplifier in each channel employs current-reuse and chopper-stabilization technology to improve power and noise performance. An output-current-tuning ripple reduction loop (RRL) is designed to reduce the intrinsic offset of the instrumental amplifier and attenuate the chopping ripple. The proposed circuit is implemented in standard 0.18 μm CMOS process. The measured mid-band gain of the front-end is 72.5/75/78.2/81 dB and the high-pass cut-off frequency is 110/150/160/210 Hz. An input-referred noise of 0.8 μVRMS (< 100 Hz), 114 dB CMRR and 102 dB PSRR are achieved at a power consumption of 7.4 μW per channel. The proposed RRL helps to suppress the chopping ripple to a level sufficiently lower than the indigenous circuit noise.
PubDate: 2019-02-12
DOI: 10.1007/s10470-019-01422-0

• A low-power low-noise amplifier with fully self-biased feedback loop
structure for neural recording
• Authors: Xianzhe Zhang; Jingyu Wang; Zhangming Zhu
Abstract: This paper presents a fully self-biased, low-power LNA for neural recordings. Due to the capacitor coupling and low-supply voltage in LNA, the appropriate dc bias voltages for saturating the input transistors NMOS and PMOS of LNA should be separately provided. This paper focuses on the effects of different feedback ways to obtain input dc bias voltage, and proposes a completely self-biased structure to obtain the bias voltage directly from the inner nodes of the circuit. This connected way avoids using extra dc biasing circuit totally, saves capacitor area effectively and reduces the high-pass corner frequency greatly. Furthermore, the proposed method eliminates the likelihood for initial DC latch-up in the traditional way, making the circuit more stable. Simulated in a 0.18-µm CMOS process, the LNA consumes 1.2 µA from a 0.6 V supply, and achieves an input referred noise of 4.98 µVrms (1–10 kHz), corresponding to a noise efficiency factor of 2.13. Simulated CMRR and THD exceed 77 dB and 75 dB, separately.
PubDate: 2019-02-11
DOI: 10.1007/s10470-019-01418-w

• Energy-efficient and two-step structure switching scheme based on
• Authors: Ruixue Ding; Shaopeng Dong; Depeng Sun; Shubin Liu; Zhangming Zhu
Abstract: A novel capacitor switching scheme for successive approximation register analogue-to-digital converters is proposed which can achieve a high energy saving, with only two references, Vref and gnd. Due to the two-step architecture is adopted here, the total capacitance is reduced by 48.44% over the conventional structure. Furthermore, based on the most-significant bit capacitor using split-capacitor procedure and monotonic switching method, the proposed switching scheme achieves 99.74% less switching energy over the conventional architecture. Note that during the design procedure, the complexity of logic and auxiliary power supply circuits are further reduced by the lack of the common voltage (Vcm). Besides the significant energy saving in the switching process, the proposed capacitor architecture also has zero consumption in reset energy. Matlab simulation results show the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.644 LSB and 0.825 LSB.
PubDate: 2019-02-11
DOI: 10.1007/s10470-019-01420-2

• A charge accumulation-free voltage-controlled functional electrical
stimulator with bi-phasic sinusoidal stimulation
• Authors: Wei-Hsien Chen; Chia-Hung Chang; Horng-Yuan Shih; Tzai-Wen Chiu; Chien-Nan Kuo
Abstract: This paper presents a charge accumulation-free voltage-controlled (VC) bi-phasic sinusoidal functional electrical stimulator (FES) for bioelectronic application. Traditionally, constant current (CC) pulse-shaped FESs with active or passive charge balancers are used to compensate for accumulated charges arise from process, voltage and temperature (PVT) variation as a result of long-term stimulation. Unlike the CC pulse-shaped FES, the VC sinusoidal-shaped FES is adopted here to avoid charge accumulation over time. The charge balancer is not required, substantially reducing system complexity and the chip area of the FES. To demonstrate the feasibility of concept, in this paper, four channels of VC bi-phasic sinusoidal-shaped FESs are integrated with the bio-potential recording circuit to compare with four channels of CC bi-phasic pulse-shaped FESs that are integrated with the same neural recording system for comparison. Measurements indicate an absence of charge accumulation as a result of the VC FESs. In addition, here we adopt the sinusoidal stimulation to reduce transient effects on tissue in comparison to a pulse-shaped method. The bio-potential activities of a cockroach leg that is stimulated for 50 s by the proposed bi-phasic sinusoidal stimulation are recorded. The measured bio-potential activities of a cockroach leg show that no stimulation-evoked leg movement occurs under stimulation by the sinusoidal waveform.
PubDate: 2019-02-09
DOI: 10.1007/s10470-019-01417-x

• Monolithic transformer and its application in a high-speed optical
interconnect VCSEL driver
• Authors: Xiangliang Jin; Xiao Xiao; Yongfeng Sun; Huayan Pu; Yan Peng; Jun Luo
Abstract: A novel vertical cavity surface emitting laser (VCSEL) driver is presented for high-speed optical interconnect. At the output stage of the driver, a transformer is used to compensate the bandwidth limitations imposed by transistors, pads and packaging parasitic. At the same time, a monolithic transformer equivalent circuit model applied in the circuit design and simulation of the VCSEL driver is proposed. Using this model, the driver has been designed and fabricated, and measurement results show that the driver with monolithic transformer compensation achieves 25% rise time and 20% fall time reduction compared to the driver without transformer. The eye diagram has been improved considerably.
PubDate: 2019-02-09
DOI: 10.1007/s10470-018-01386-7

• A 171 GHz harmonic-mode PLL with − 14.2 dBm output
power in 65 nm CMOS
• Authors: Sanjeev Jain; Leonid Belostotski
Abstract: This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating at 171 GHz provides − 14.2 dBm output power and a spur level of − 67.5 dBc. The PLL is built with a varactor-free 2fO VCO, which is tuned by varying transistor intrinsic capacitances via MOS bulk voltages.
PubDate: 2019-02-04
DOI: 10.1007/s10470-019-01413-1

• An autonomous chaotic and hyperchaotic oscillator using OTRA
• Authors: Manoj Joshi; Ashish Ranjan
Abstract: This research paper reports a novel design for third order chaotic and hyperchaotic oscillator with cubic nonlinearity using single operational trans-resistance amplifier (OTRA) and few passive elements. The key nonlinear dynamical characteristics in terms of sensitivity, divergence, equilibrium point and Lyapunov exponent are recorded in this literature. The operational activity of the proposed oscillator based on OTRA is integrated using 0.25 µm TSMC CMOS parameter. For the generation of hyperchaotic oscillator, an external capacitor is added to the third order chaotic oscillator. To justify the theoretical nonlinear dynamics of proposed chaotic oscillator, PSPICE simulation by using CMOS based OTRA and experimental investigation using IC AD844 based OTRA are well implemented.
PubDate: 2019-02-04
DOI: 10.1007/s10470-019-01395-0

JournalTOCs
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Email: journaltocs@hw.ac.uk
Tel: +00 44 (0)131 4513762
Fax: +00 44 (0)131 4513327