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 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [7 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2351 journals]
• Design techniques for mitigation of intermodulation distortion components
in CMOS RF receiver front-end circuits with subthreshold operation
• Authors: Chun-hsiang Chang; Li Xu; Marvin Onabajo
Pages: 335 - 346
Abstract: This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a − 10.8 dBm IIP3 with a power consumption of 0.9 mW.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1060-x
Issue No: Vol. 94, No. 3 (2018)

• Design considerations of CMOS active inductor for low power applications
• Authors: Jack Ou; Pietro M. Ferreira
Pages: 347 - 356
Abstract: Previous studies have shown that $$g_m/I_D$$ (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in $$0.18\,\upmu \hbox{m}$$ CMOS process and show that by systematically working through sizing issues, a $$10\,\upmu \hbox{A}$$ sub GHz amplifier can be designed.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1059-3
Issue No: Vol. 94, No. 3 (2018)

• Design and analysis of a feedback time difference amplifier with linear
and programmable gain
• Authors: Wenlan Wu; R. Jacob Baker; Phaneendra Bikkina; Yu Long; Andrew Levy; Esko Mikkola
Pages: 357 - 367
Abstract: This paper proposes a feedback time difference amplifier (FTDA) that achieves linear, controllable gain and changeable input range for different time difference gains. The proposed FTDA consists of two identical feedback output generators. The feedback output generator achieves a linear input–output transfer characteristic by employing two p-type keepers for time gain feedback control. Its validity was demonstrated using $${0.13}\, {\upmu \hbox {m}}$$ SiGe BiCMOS process. The power consumption is $$91.54 \,{\upmu \hbox {W}}$$ for the highest gain with input signals at $${2}\,\hbox {MHz}$$ . The gain can be controlled from 25.06 to $$734.9\,{\hbox {s/s}}$$ within $$40 \,\hbox {ps}$$ input time interval.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1062-8
Issue No: Vol. 94, No. 3 (2018)

• A LIDAR sensor prototype with embedded 14-bit 52 ps resolution
ILO-TDC array
• Authors: Chih-Yuan Chen; Cheng Li; Marco Fiorentino; Samuel Palermo
Pages: 369 - 382
Abstract: High resolution light detection and ranging (LIDAR) systems enable rapid imaging and mapping for applications such as autonomous vehicles and robotics. This paper presents a high-resolution LIDAR sensor system-on-a-chip (SoC) prototype containing a 31 × 2 pixel channel array with the input time-of-flight resolved by a 32 × 1 time-to-digital converter (TDC) array. A low-power avalanche photodiode (APD) receiver front-end with output bit-line sharing allows an array implementation and achieves − 22 dBm sensitivity. Injection-locked oscillators (ILOs) are utilized in a TDC design to both minimize clock distribution power and improve timing accuracy. An on-chip phase-looked loop calibrates for ILO global PVT variations and ensures reliability over a wide operating range. Fabricated in GP 65 nm CMOS, the 14-bit TDC consumes 788 μW/channel and achieves 52 ps resolution over an 830 ns full-scale range, 37.2 psrms single-shot precision, 11 psrms channel uniformity, and DNL/INL of 0.56/1.56 LSB, respectively. This electrical characterization projects that the SoC has the potential for 0.78 cm ranging precision over a 124 m maximum ranging distance. Sensor testing with a pulsed laser and an APD array hybrid-integrated with the CMOS SoC shows a measurement range of over 700 ns with a 3.2 ns maximum single-shot error.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1067-3
Issue No: Vol. 94, No. 3 (2018)

• Neural network based real-time heart sound monitor using a wireless
wearable wrist sensor
• Authors: W. Y. Shi; J.-C. Chiao
Pages: 383 - 393
Abstract: A new method is presented using a wearable wrist sensor to estimate acoustic parameters S1 and S2 of the heart sounds based on the neural network technique. Using the signal processing method, the heart conditions can be analyzed and monitored in real time and potentially in a long term with a wrist device. The velocities and time delays of the cardiac pulse waves in blood vessels were experimentally acquired and calculated at different artery locations on the human body. Signal attenuation of the pulses from the heart to the wrist radial artery was analyzed and a pulse-waveform travel model in blood vessels was proposed. A band-pass filter is applied to the pulse waves at various artery locations to reveal the heart sound features S1 and S2 existed in the pulse waves. In order to obtain accurate acoustic parameters, a neural network with two layers and 500 nonlinear tansig neurons was employed to estimate the heart sounds using the pulse waveforms from the wrist radial artery. It is encouraging to find that the acoustic parameters of estimated heart sounds by the trained neural network have only 1% average errors compared with the original heart sounds. The effects of various analog-to-digital conversion resolutions and sample rates were empirically analyzed. When the maximum value of errors is allowed within 2.15%, a 10,000-Hz sample rate and 12-bit resolution should be an appropriate selection for lower power consumption. Using the trained neural network, the new estimation method has been verified by a sensor with Bluetooth communication strapped on the wrist, thus mobility is not limited for the person whose heart sounds need to be monitored.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1056-6
Issue No: Vol. 94, No. 3 (2018)

• Contactless hand tremor detector based on an inductive sensor
• Authors: W. Y. Shi; J.-C. Chiao
Pages: 395 - 403
Abstract: A contactless detector is presented for evaluating hand tremors caused by exercise-induced fatigue and early Parkinson’s disease. The device consists of a spiral coil, a microcontroller, and an inductive sensor circuitry. Theory shows that the resonant frequency of the circuitry increases when the distance between the hand and the spiral coil decreases, thus small variations of distance from tremor can be detected from the changes of resonant frequencies. A mechanical hand was built for experiments to simulate human hand tremors with repeatability at a fixed frequency. The magnitudes and frequencies of the tremors in the mechanical hand were quantitatively identified using the inductive sensor. Hence, feasibility and accuracy of the contactless hand tremor detector were determined. A triaxial accelerometer was used for comparison. By comparing spectral distributions and magnitudes of the tremors, the inductive sensor performed better than the accelerometer. The detector was applied to evaluate actual hand tremors of three subjects who had undergone exercise to induce tremors. The tremor waveform amplitudes of the subjects were quantitatively analyzed by the standard deviations method. The increased signal energies of exercise-induced tremor within 8–12 Hz were confirmed. Then, a subject with early Parkinson’s disease was evaluated by the proposed hand tremor detector. The tremor magnitudes and frequencies of the patient hand were quantitatively identified within in 4–7 Hz. Therefore, the new contactless hand tremor detector can be developed as a clinical instrument for monitoring the fatigue symptoms of post-exercise and diagnosing the early Parkinson’s disease.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1055-7
Issue No: Vol. 94, No. 3 (2018)

• Optimal dynamic range scaling of ΔΣ ADC using bias current
estimation
• Authors: Youngho Jung; Gabor C. Temes
Pages: 405 - 412
Abstract: In this paper, optimal dynamic range scaling of ΔΣ ADC using bias current estimation method is proposed. Generally, a different dynamic range scaling gives different feedback factor and effective load capacitance to each integrator in the ΔΣ ADC. It means that power consumption of each integrator strongly depends on the coefficient of the integrator. Therefore, the proposed method estimates which dynamic range scaling consumes the least power to achieve a given settling error. To verify the effectiveness of the proposed method, the noise coupled third order ΔΣ ADC having different dynamic scaling with transistor level opamps was simulated to compare the ADC performance.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1102-4
Issue No: Vol. 94, No. 3 (2018)

• Ultra-low-power bulk-driven fully differential subthreshold OTAs with
partial positive feedback for G m -C filters
• Authors: Tripurari Sharan; Priyanka Chetri; Vijaya Bhadauria
Pages: 427 - 447
Abstract: This paper presents an ultra-low-power, bulk-driven, source-degenerated fully differential transconductor (FD-OTA), operating in subthreshold region. The source-degeneration (SD) and bulk-drive ensure linearity and rail-to-rail input swing. The flipped voltage follower and SD resistor perform V–I conversion in input core with power efficient class AB mode of operation. The reduction in open loop gain and gain bandwidth (GBW) of bulk-drive is compensated by applying partial positive feedback at diode connected MOSFET pair. The current gain from input core to output load side is set (1:1) in OTA1 and (1:4) in OTA2. The OTA2 offers increased transconductance and GBW whereas self-cascode load increases the output impedance and overall gain of the FD-OTAs. Both the input core and common source self-cascode load operate in class AB mode so these FD-OTAs provide enhanced slew rates. These OTAs have been employed to implement Biquadratic low-frequency Gm-C filter suitable for bio-signal applications. The proposed OTA2 has used dual supply voltage of ± 0.3 V and dissipates around 70 nW power and provides 62 dB FD-open loop gain with GBW of 7.73 kHz while driving the FD-load of 2 × 15 pF. The Cadence VIRTUOSO environment using UMC 0.18 µm CMOS process technology has been used to simulate the proposed circuit. The Simulation results verified fully differential total harmonic distortion of − 72 dB, for 1.2 Vp–p signal at 200 Hz frequency in unity gain configuration with resistive degeneration of 1 MΩ for OTA1.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1065-5
Issue No: Vol. 94, No. 3 (2018)

• Correction to: Ultra-low-power bulk-driven fully differential subthreshold
OTAs with partial positive feedback for G m -C filters
• Authors: Tripurari Sharan; Priyanka Chetri; Vijaya Bhadauria
Pages: 449 - 449
Abstract: The original version of this article unfortunately contained a mistake. The presentation of Fig. 3 was incorrect. The correct version of Fig. 3 is given.
PubDate: 2018-03-01
DOI: 10.1007/s10470-018-1121-9
Issue No: Vol. 94, No. 3 (2018)

• A wideband receiver front-end using 1st and 3rd harmonics of the N -path
filter response
• Authors: Mohammad Elmi; Mahdi Tavassoli; Ali Jalali
Pages: 451 - 467
Abstract: Harmonic selectivity and inaccessibility to accurate low-power high frequency clock generator are two main imperfections in the tunable N-path filters. In this paper, conventional N-path filter and conventional harmonic rejection (HR) N-path architectures are analyzed, and related equations are derived and are verified by simulation results. Furthermore, a wideband tunable receiver front-end using HR N-path switching systems is proposed. Using third harmonic of filter response instead of fundamental harmonic, the required input clock frequency in the multi-phase clock generator is decreased by a factor of three. The receiver front-end benefits low and high frequency bands. At low frequency band (0.4–1.2 GHz) the first harmonic, and at high frequency band (1.2–3.3 GHz) the third harmonic of filter response are selected and are downconverted to the baseband frequency. The structure is designed and is simulated using CMOS-90 nm technology in schematic level. The total power consumption and $$S_{11}$$ are $$<27.14$$  mW and $$-13.5$$  dB, respectively. Furthermore, NF at low and high frequency bands are 2.56 and 3.53 dB, respectively.
PubDate: 2018-03-01
DOI: 10.1007/s10470-017-1096-y
Issue No: Vol. 94, No. 3 (2018)

• A compact and high performance dual-band bandpass filter based on
unbalanced composite right/left-handed transmission lines for WLANs
applications
Pages: 469 - 479
Abstract: In this paper, a novel compact microstrip dual-band (DB) bandpass filter with high selectivity for wireless local area networks applications is proposed. The design procedure is based on unbalanced composite right/left-handed (UCRLH) transmission lines (TLs). The DB features can be achieved by unbalancing the CRLH transmission line. The necessary conditions to obtain a discontinuous transition between the left- and right-handed bands, intended to provide UCRLLH TL, are investigated. The application of this technique to design of compact DB filters is illustrated. The structure of the proposed DB filter is implemented by a series interdigital capacitor located between two microstrip lines that shorted to the ground plane by vias. The vias with microstrip lines acting as a shunt connected inductor while the series capacitor is realized by interdigital capacitor. The design procedure based on a simple equivalent circuit is also introduced. The proposed filter has advantages such as compact size, easy fabrication, high selectivity, low insertion loss, high return loss and, design flexibility. To validate the proposed technique, the proposed DB filter has been fabricated and tested. Good agreement has been found between simulation and measurement results. The total size of the proposed UCRLH DB filter is 0.17 λg × 0.048 λg, where λg is the guided wavelength of the lower pass-band. The size of the proposed DB filter is more compact in comparison with known similar filters.
PubDate: 2018-03-01
DOI: 10.1007/s10470-018-1104-x
Issue No: Vol. 94, No. 3 (2018)

• Graphene oxide: Nylon ECG sensors for wearable IoT
healthcare—nanomaterial and SoC interface
• Authors: N. G. Hallfors; M. Alhawari; M. Abi Jaoude; Y. Kifle; H. Saleh; K. Liao; M. Ismail; A. F. Isakovic
Abstract: The Internet of Things (IoT) presents opportunities to address a variety of systemic, metabolic healthcare issues. Cardiovascular disease and diabetes are among the greatest contributors to premature death worldwide. Wireless wearable continuous monitoring systems such as ECG sensors connected to the IoT can greatly decrease the risk of death related to cardiac issues by providing valuable long-term information to physicians, as well as immediate contact with emergency services in the event of a heart attack or stroke. In this report we discuss the fabrication, characterization and validation of composite fabric ECG sensors made from Nylon® coated with reduced graphene oxide (rGOx) as part of a self-powered wearable IoT sensor. We utilize an electronic probing station to measure electrical properties, take live ECG data to measure signal reliability, and provide detailed surface characterization through scanning electron microscopy. Finally, bonding between the layers of the composite and between composite and the Nylon® is analyzed by Fourier transform Infrared spectroscopy. Furthermore, a low power analog front end circuit designed in 65 nm CMOS process is presented to interface the sensor with a system on chip used in a wearable IoT healthcare device.
PubDate: 2018-02-26
DOI: 10.1007/s10470-018-1116-6

• Determinant characteristics in EEG signal based on bursts amplitude
segmentation for predicting pathological outcomes of a premature newborn,
with validation using ANN
• Authors: Yasser Al Hajjar; Abd El Salam Al Hajjar; Bassam Daya; Pierre Chauvet
Abstract: EEG signal contains some specific patterns that predict neuro-developmental impairments of a premature newborn. Extracting these patterns from a set of EEG records provides a dataset to be used in machine learning in order to implement an intelligent classification system that predict prognosis of the baby. In a previous work we proved that inter-burst intervals (IBI) found in the EEG records predicts abnormal outcomes of the premature. A bibliographic study on the amplitude of an EEG signal, with the annotations of the neuro-pediatricians, showed that low amplitudes in EEG signal are strongly correlated with an abnormal prognosis of the premature, similar to that of IBI. According to these hypotheses, we present in this paper, a segmentation methodology on the amplitude of bursts intervals of EEG signal into 3 segments: low, medium and high, in addition to the inter-burst intervals. We create a new algorithm that detects 6 important parameters in each interval of these 4 segments. After applying this new methodology, we obtain a new classified dataset that contains 24 parameters extracted from these 4 segments to obtain with gestational age of the preterm and the day of recording 26 input attributes and one output which is the class (normal, sick or risky). Finally we validate the pertinence of these attributes using artificial neural network.
PubDate: 2018-02-24
DOI: 10.1007/s10470-018-1129-1

• Smart water technology for leakage detection: feedback of large-scale
experimentation
• Authors: Elias Farah; Isam Shahrour
Abstract: Recent advances in intelligent water meter technology have improved the quantitative monitoring in water supply and distribution systems. Smart meters using automated meter reading (AMR) technology allow water utilities to: (a) provide clear consumption patterns which can help customers to track and control their water usage and (b) improve active leakage targeting and leak detection capability. This paper presents a feedback about the use of AMR system to detect leakage in a large-scale experimentation, which is conducted at the Scientific Campus of the University of Lille, which stands for a small town of 25,000 users. This paper presents the demonstration site as well as its monitoring using AMR technology and how this technology allowed a rapid detection of water leakage.
PubDate: 2018-02-24
DOI: 10.1007/s10470-018-1137-1

• Selected papers from the IEEE Dallas circuits and systems conference 2016
• Authors: Sid Balasubramanian; Ranjit Gharpurey; Rama Venkatasubramanian
PubDate: 2018-02-05
DOI: 10.1007/s10470-018-1115-7

• 4-to-1 Transimpedance combining amplifier-based static unitary detector
• Authors: Eun-Gyu Lee; Jae-Eun Lee; Minhyup Song; Gyu Dong Choi; Bongki Mheen; Bang Chul Jung; Choul-Young Kim
Abstract: A fully integrated 4-to-1 transimpedance combining amplifier (TICA)-based static unitary detector (STUD) is developed for high-resolution of laser detection and ranging (LADAR) sensor. With a developed TICA, the STUD is able to have an effective large-area photodetector to enlarge the region of interest (ROI) without the bandwidth deterioration of a receiver for LADAR sensor. The 4-to-1 TICA is fabricated using 0.18-μm standard CMOS technology and it consists of four independent current buffers, a two-stage signal combiner, a balun, an output buffer, and four over-current protectors in one single integrated chip. The core of the TICA dissipates a power of about 7.8 mW. The total power consumption, including that of the balun and the output buffer, is 41 mW from a 1.8-V supply. The average input-referred noise current spectral density is 15.4 pA/√Hz with a bandwidth of 185 MHz and a transimpedance gain of 70 dBΩ. The developed TICA occupies an active area of approximately 107 μm × 102 μm and the die size, including the I/O pads, is 912 μm × 1000 μm. From the two-dimensional optical pulse scanning measurements and the three-dimensional (3-D) range measurements, it is verified that the designed TICA is suitable for the receiver front-end of the STUD-based LADAR sensor.
PubDate: 2018-01-25
DOI: 10.1007/s10470-018-1112-x

• A fast-locking low-jitter digitally-enhanced DLL dynamically controlled
for loop-gain and stability
• Authors: Sarang Kazeminia; Roozbeh Abdollahi; Arash Hejazi
Abstract: Conventional structure of delay locked loops (DLLs) is modified to achieve better jitter and smaller lock time. In the proposed structure, analog charge pump is eliminated, to remove the problems of leakage current on output capacitance, and is replaced by combination of a digital accumulator (ACC) and a digital-to-analog converter. A programmable ACC is also proposed, to dynamically control the loop gain and lock time. When the loop enters to lock region at the first time, a lock detector block disables ACC and equivalent digital code is stored on a latch array. So, a fixed control voltage controls delay elements and the systematic jitter, due to periodic discharge of control voltage. RMS jitter of less than 33.5 and 1.6 ps are achieved at 20 and 625 MHz operating frequencies, respectively, when the supply is subject to 110 mV random noise and also 40 mV periodic noise, related to generated clock signals. Lock time is reduced from 38 to 2 µs at 20 MHz, and also from 900 to 45 ns at 600 MHz, when the proposed dynamic control mechanism is applied on the loop. Total power consumption for the main core of DLL is 7.85 mW at 1.8 V supply in 0.18 µm CMOS process.
PubDate: 2018-01-24
DOI: 10.1007/s10470-018-1109-5

• 99.83% Switching energy reduction over conventional scheme for SAR ADC
without reset energy
• Authors: Xin Xin; Jueping Cai; Ruilian Xie
Abstract: A high-efficient switching method for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. With the proposed variable resolution SAR ADC architecture, the average switching energy and area can be reduced by 99.60 and 73.54% respectively compared to the conventional scheme. Combined with C–2C capacitor array and unilateral monotonic scheme, the proposed two-step architecture achieves 99.83% less average switching energy and 76.37% less area reduction over the conventional approach. Furthermore, these two methods have no rest energy consumption.
PubDate: 2018-01-23
DOI: 10.1007/s10470-018-1113-9

• A robust and low-power near-threshold SRAM in 10-nm FinFET technology
• Authors: Sina Sayyah Ensan; Mohammad Hossein Moaiyeri; Shaahin Hessabi
Abstract: This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.
PubDate: 2018-01-22
DOI: 10.1007/s10470-018-1107-7

• Digital extraction of quantization error and its applications to
successful design of sigma-delta modulator
Abstract: A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and cancelled out by adding a digital subtractor and by injecting a purely analog signal from the preceding stage to the next stage. In comparison to conventional MASH modulator structure, analog circuit requirements of the modulator are therefore relaxed, and the number of switched-capacitor digital-to-analog converters and the associated switching energy are lowered. In the absence of extra switching blocks, less flicker and thermal noise would be also injected into the circuit. Different implementations of MASH modulator are presented and analyzed based on the proposed digital quantization error extraction technique. Behavioral-level simulation results prove the mathematical equivalence of the proposed structures with successful MASH designs found in the literature, and confirm the effectiveness of the idea. For a − 1.4 dB, 19.8 kHz input and an oversampling ratio of 16, a modified 1-V 20-MS/s 2 + 2 MASH modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 78 dB, when the input of the first quantizer is fed to the second stage. The second design based on digital extraction of quantization error achieves a 71 dB SNDR for a − 8.0 dB, 19.8 kHz input, when the second stage is fed by the output of the first integrator.
PubDate: 2018-01-22
DOI: 10.1007/s10470-018-1108-6

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