Authors:Bilgin Metin; Oguzhan Cicekoglu; Serdar Ozoguz Pages: 5 - 13 Abstract: Abstract In this paper, a set of current-mode MOSFET-C multifunction filters are presented. Since MOS transistors operating in saturation region are used instead of the passive resistors, key filter parameters are all electronically controllable. The main properties of a total of eight different multifunction filters are catalogued in tabular form. The proposed circuits exhibit attractive features such as circuit simplicity and reduced chip area compared to the classical analog filters that require active elements including large number of transistors. All the filters are simulated in spectre simulation software in Cadence design environment using 90 nm UMC CMOS process parameters. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1272-8 Issue No:Vol. 97, No. 1 (2018)

Authors:Elham Minayi; I. Cem Göknar Pages: 15 - 25 Abstract: Abstract A new kind of metamutator, namely “Current Inverting Metamutator”, its realizations using different types of active blocks and some of its applications like voltage-mode universal biquadratic filter with three input and one output terminals are presented. The proposed circuits can realize all standard filters, namely, low-pass, band-pass, high-pass, notch and all-pass without passive component matching conditions. The proposed circuit offers the features of using grounded capacitors and orthogonal controllability of angular frequency and quality factor. Then a novel realization of metamutator with one active device, additive and differential IC (AD-IC) is proposed and implemented with twelve transistors only. The metamutator with AD-IC has the advantages: (1) of creating new realizations of memristors, capacitance multipliers, inductor simulators, frequency dependent negative resistors which can be used to make IC active filters, (2) less is the number (only one) of active devices, less is the amount of disparity, (3) no need to match passive component values. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1239-9 Issue No:Vol. 97, No. 1 (2018)

Authors:Ali Dogus Gungordu; Nil Tarim Pages: 27 - 38 Abstract: Abstract In this study, a constant-bandwidth variable-gain amplifier (VGA) is presented for long-term evolution (LTE) receivers. The presented VGA’s description is given with a newly proposed exponential-current generator, and also the common-mode feedback and the DC-offset cancellation (DCOC) circuits. The proposed exponential current generator is based on the Taylor series approximation in such a way that it can be expanded to meet the required gain control range. The simulations are performed using the TSMC 180 nm process technology with Cadence Analog Virtuoso. The VGA has a 45 dB gain control range, 180 MHz bandwidth, 15.7 dB m the third-order input-intercept point for minimum gain and below 20 dB noise figure for maximum gain which makes it convenient for LTE receivers. The simulations also show that the bandwidth of the VGA is fairly constant over the control range. Monte Carlo simulations reveal that by using a DCOC circuit, the VGA provides 30 dB output offset rejection. The overall power consumption of the circuit is 9.1 mW under a 1.8 V power supply. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1237-y Issue No:Vol. 97, No. 1 (2018)

Authors:Mustafa Tarık Saniç; Mustafa Berke Yelten Pages: 39 - 47 Abstract: Abstract In this paper, a methodology to analyze the time dependent dielectric breakdown (TDDB) reliability of CMOS analog and radio frequency (RF) circuits has been proposed and applied to common circuit building blocks, including an operational amplifier, a RF mixer, and a comparator. The analysis includes both finding the transistors in the circuit topology that are the most sensitive to TDDB degradation, as well as, observing the trends of TDDB degradation over a series of nanoscale process technologies for each building block. Analysis outcomes suggest that the TDDB degradation resilience goes up for operational amplifiers and comparators whereas it decreases for RF mixers as the device channel lengths come down. The trends have been explained on the basis of the circuit block topology and device physics. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1243-0 Issue No:Vol. 97, No. 1 (2018)

Authors:M. Sait Altuner; Metin Yazgi; Ali Zeki; Hadi G. Momen; Ali Toker Pages: 49 - 57 Abstract: Abstract In this paper, a new pseudo-exponential function is described and a new CMOS exponential-control variable gain amplifier (VGA) based on the new function is introduced. No multiplier is needed in the proposed approach. The VGA operates in current mode and includes two different stages. The first stage is a simple current amplifier while the second stage is an attenuator. The overall behavior of the stages gives the new pseudo-exponential function. The VGA circuit has been designed and simulated for a 0.18 μ CMOS process. Post layout results show that the circuit has a bandwidth of 164 MHz and a gain range of 32.5 dB between − 21 and + 11.5 dB. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1234-1 Issue No:Vol. 97, No. 1 (2018)

Authors:Hacer Atar Yildiz Pages: 59 - 68 Abstract: Abstract In this paper, it is aimed to realize a systematic approach for the realization of the MOS only complex polyphase filters which occupy small chip area. For this purpose, we used a technique based on adding cross-coupled transistors realizing local positive feedback, which, in turn, increases filter time constants. Thanks to this method, a substantial reduction in the filter chip area is achieved without having to use bulky on chip capacitors. The usefullness of the approach is validated by comparing the layouts of the designed CMOS circuit with the conventional RC polyphase filter. Post-layout simulation results using SPECTRE in CADENCE design environment are provided to verify feasibility of the proposed complex filter. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1271-9 Issue No:Vol. 97, No. 1 (2018)

Authors:Omer Aydin; Tayfun Aydin Pages: 69 - 74 Abstract: Abstract Recognizing that the ratio of the peaking and main amplifier transconductances is a crucial parameter in the design of Doherty power amplifiers, we propose an analytical method to specify the optimum value of this ratio. The method is validated both through simulations based on circuit-level model of the Doherty power amplifier and the experiments using a 100 W dual driven symmetrical LDMOS Doherty power amplifier manufactured. According to the experiments, overdriven peaking amplifier is resulting in lower drain voltage at the main side, hence causing low power efficiency. Conversely, underdriven peaking amplifier is saturating the main amplifier, which in turn results in decreased linearity. Both simulation and experimental results clearly revealed that the amplifier efficiency and linearity strongly depend on the drive levels of the main and peaking amplifiers. The third-order intermodulation distortion of a 44 dBm and 2.655 GHz Doherty power amplifier which is measured as − 29.75 dBc in the overdriven case, is increased up to − 19.40 dBc in the underdriven case. However, the drain efficiency which is measured at 47.84% in the overdriven case is improved to 54.36% when the peaking amplifier is operated in the underdriven mode for 47 dBm and 2.655 GHz. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1202-9 Issue No:Vol. 97, No. 1 (2018)

Authors:Noushin Ghaderi; Erfan Allasvand; Abouzar Mohammadi; Saman Kamran Pages: 75 - 85 Abstract: Abstract In this paper, an efficient modulation technique, which was a new combination of multi-pulse position modulation (MPPM) and pulse amplitude modulation methods, was introduced. Using the proposed modulation, 8-bit per symbol data rate was achieved. Applying this method increased the data rate value and reduced the power consumption value. In addition, due to the use of MPPM method in the proposed modulation, the generated signal was of the return-to-zero nature. This means that the clock signal was embedded inside the modulated signal. Therefore, there was no need to apply a complicated clock recovery circuit in the receiver side. Moreover, by sending the 8-bit data and clock signal through a single channel, the value of pin count was reduced considerably. To implement this new scheme, a new transceiver was proposed in this paper. Further, a very simple slot selector circuit was proposed to create 5-time slots per symbol. In addition, a new structure of absolute comparator circuit was designed to reduce the number of comparators at the receiver side. The whole power dissipation of the proposed transceiver was only 101 mW. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1233-2 Issue No:Vol. 97, No. 1 (2018)

Authors:Ersin Alaybeyoğlu; Hakan Kuntman Pages: 87 - 96 Abstract: Abstract In this study, a new implementation of reconfigurable analog baseband (ABB) low pass filter employing cell-based variable transconductance amplifier (cell-based VTA) is presented for multi-standard transceivers. The configurability of the designed filter is supported by activating different cells and changing biasing currents of each cell. Multi-standard transceivers allow to process different protocols in a single chip. These type transceivers need reconfigurable analog elements. In this work reconfigurable ABB low-pass filter is designed to support the application of Bluetooth, CDMA2000, Wideband CDMA, and IEEE 802.11a/b/g/n wireless LANs and 2G/3G/4G. The designed filter operates between 20 kHz and 40 MHz. The minimum value of the designed filter’s third order intersection point is 21.4 dBm. The performance of the designed circuit is tested with TSMC 0.18 µm technology in CADENCE environment. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1241-2 Issue No:Vol. 97, No. 1 (2018)

Authors:Deniz Ozenli; H. Hakan Kuntman Pages: 97 - 105 Abstract: Abstract A novel current mode MOSFET-C filter is presented for a wide range of low frequency applications ranging from biomedical signal sensing up to speech processing region. Presented filter consumes only 2.3 µW with symmetrical supply voltages as low as ± 0.5 V. The filter structure can be easily adjusted by means of changing external capacitor values. Furthermore, proposed filter is given with a novel design methodology based on polynomial regressive small signal models. In this way, promising interaction between design parameters such as VGS, VDS, channel width (W), channel length (L) and filter specifications such as f0, Q and power is provided. Simulation results with 0.18 µm TSMC CMOS technology are given, furthermore proposed filter is tested to process a real fetal PCG signal at 355.4 Hz. It is shown that proposed filter attains a promising performance in comparison with the previously presented counterparts for low frequency applications. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1227-0 Issue No:Vol. 97, No. 1 (2018)

Authors:Jaroslav Koton; David Kubanek; Norbert Herencsar; Jan Dvorak; Costas Psychalinos Pages: 107 - 114 Abstract: Abstract Once designing analogue fractional-order function blocks, the capacitive and/or inductive fractional-order elements (FOEs), also referred to as constant phase elements, being defined with their fractional order \(\alpha\) ( \(0< \alpha < 1\) ) are required. Although currently capacitive FOEs are being discussed in the literature, still these passive elements are not readily available in discrete form and mainly do not offer the whole span of \(\alpha\) . Therefore, to overcome such an obstacle, we primary propose the transformation of FOEs and their fractional order \(\alpha\) to obtain the complement order \(\beta\) , whereas \(\beta =1{-}\alpha\) . Following the theory and mathematical description, also other transformation cases on fractional-order element are discussed and analysed in this paper. Using simple impedance converter employing single current conveyor and transconductance amplifier, the theoretical presumptions are verified both by simulations and experimental measurements. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1257-7 Issue No:Vol. 97, No. 1 (2018)

Authors:Ruixue Ding; Depeng Sun; Shubin Liu; Hongzhi Liang; Zhangming Zhu Pages: 115 - 122 Abstract: Abstract A high energy-efficiency capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters is proposed in the paper. During the design procedure, the charge characteristic of the floating capacitor and the technique of splitting capacitor ensure zero energy consumption of switching operation. With the reset energy of capacitor arrays taken into account, the proposed switching scheme can achieve 100% less switching energy over the conventional switching scheme. Furthermore, this work also achieves about 50% area reduction with only two reference voltages. The behavioral simulation of the proposed SAR was performed, the maximum differential nonlinearity and maximum integral nonlinearity are 0.451 and 0.452 LSB respectively. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1242-1 Issue No:Vol. 97, No. 1 (2018)

Authors:B. Ghanavati; E. Abiri; A. Keyhani; M. R. Salehi; A. Sanyal Pages: 123 - 133 Abstract: Abstract A new capacitor switching scheme with considerable energy saving for successive approximation register (SAR) analog to digital converter (ADC) is presented. Employing different switching sequence and also one switching event in a cycle in this technique, result in 97.67% reduction in switching energy. Besides that, in the proposed method, an 8 × reduction in total capacitance compared to the conventional architectures achieved by benefiting from LSB split capacitor array. Furthermore, the proposed technique shows the minimum power dissipation in driving the switches since it has only one switching event per cycle and lowest capacitor array compared to the other techniques. Employed the proposed switching scheme, a 10-bit 1-kS/s SAR ADC is designed in 0.18-µm CMOS technology with an active area of 0.025 mm2. With a 1-V power supply for analog and 0.5-V for digital circuit, the ADC achieves an ENOB of 9.73 bits and a FoM of 4.1 fJ/conversion-step. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1250-1 Issue No:Vol. 97, No. 1 (2018)

Authors:Cheng Huang; Jianhui Wu; Chunfeng Bai Pages: 135 - 141 Abstract: Abstract This paper analyzes high linearity Cherry–Hopper programmable-gain-amplifier (PGA), which is a cascade of linear transconductance (Gm) stage and transimpedance (TIA) stage. Basing on these analysis, reasons for gain peaking of Gm–TIA PGA are discussed. A Gm–TIA PGA with flat gain response and high power-efficiency is designed, and implemented in a 0.18 μm CMOS process. It draws 260-μA current from a supply of 1.8-V, while maintains a constant bandwidth of 24-MHz when driving a capacitive load of 2-pF. Flat gain response over the gain range is obtained, and the measured OIP3 reaches 19.5 dBm. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1265-7 Issue No:Vol. 97, No. 1 (2018)

Authors:Seung-Uk Baek; Se-Won Lee; Kang-Yoon Lee; Minjae Lee Pages: 143 - 148 Abstract: Abstract An energy-efficient scaled-down reference (SDR) digital-to-analogue converter switching sequence is presented for a low-power successive approximation register analogue-to-digital converter. Owing to the fact that the proposed technique utilizes only a quarter of the capacitor array for input sampling, an SDR (Vref/4) and ground (Gnd) for the same input are required for conversion cycles, which achieve reduced switching energy and high linearity. The SDR switching structure improves the efficiency of average switching energy by 99.61% and reduces the total number of required capacitors in the digital-to-analogue converter arrays by 50% compared to the conventional structure. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1279-1 Issue No:Vol. 97, No. 1 (2018)

Authors:D. R. Bhaskar; Manoj Kumar; Pragati Kumar Pages: 149 - 158 Abstract: Abstract Two new op-amp-based multifunction filter structures are proposed which can realize fractional order inverse low pass, high pass and band pass filters. In the first configuration, op-amp is used in an inverting mode while in the second structure op-amp is employed in non-inverting mode. To the best knowledge of the authors, any fractional order inverse filter structure employing any active element/device has not been reported in the open-literature so far. The proposed inverse filters have been simulated in PSPICE using µA741-type op-amp as well as in MATLAB to validate the theoretical propositions. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1287-1 Issue No:Vol. 97, No. 1 (2018)

Authors:Mohammad Jafar Hemmati; Rasoul Dehghani; Ahmad Hakimi; Sajad Naderi Nejad Pages: 159 - 168 Abstract: Abstract In this work, a new differential topology of Colpitts VCO with an enhanced transconductance is presented. The proposed circuit is consisted of an NMOS and a PMOS differential Colpitts cores configured as complementary, and also an LC resonator. The VCO is designed to oscillate at 5 GHz which consumes 1.11 VA from 1.4 V supply voltage. In addition, a modified version of the proposed VCO is designed for lower power applications. This circuit employs new positive feedbacks to enhance the VCO’s transconductance and reduce the supply voltage. The modified VCO operates with 1.1 V power supply while dissipating 1 mW. To investigate the performance of the proposed circuits, the transconductance of them are theoretically analyzed. Also, two new quadrature VCOs (QVCOs) are presented which are realized by two identical latter proposed Colpitts VCOs. A linear analysis is presented to confirm that the first oscillator can generate outputs with 90° phase differences. The proposed circuits are designed in 0.18-μm RF-CMOS technology. Finally, prototype circuits of the proposed VCOs are fabricated to validate the theoretical results. The measurement results are summarized to demonstrate the main features of the proposed oscillators. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1288-0 Issue No:Vol. 97, No. 1 (2018)

Authors:Jian Liu; Shubin Liu; Lei Huang; Zhangming Zhu Pages: 169 - 176 Abstract: Abstract In this letter, a highly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is presented with the redundant capacitance splitting technology. The redundant capacitance splitting technology is put forward innovatively to divide the convert cycles into two parts: high bits cycles and low bits cycles. And through a simple switch, the redundant capacitance is split off from the capacitance array in the high bits convert cycles, resulting in the improvement of SAR ADC performance. With the monotonic mode, the first bit cycle and the second bit cycle are completed without consuming any switching energy. The proposed novel switching scheme can achieve 99.54% less switching energy and 75% reduction in capacitor area compared with the conventional switching scheme for SAR ADC, respectively. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1302-6 Issue No:Vol. 97, No. 1 (2018)

Authors:Rakesh Verma; Neeta Pandey; Rajeshwari Pandey Pages: 177 - 191 Abstract: Abstract This paper presents higher order fractional element using the concept of impedance inverter circuit based on operational transcoductance amplifier (OTA). Firstly the concept of OTA impedance inverter is generalized in fractional domain which is followed by presentation of novel OTA based inverted impedance multiplier circuit (IIMC) and its generalization. Effect of OTA parasites on performance of proposed IIMC is also presented. The usefulness of the proposal is illustrated through implementation of fractional order filter of higher order using IIMC. The functional verification of all proposed circuits is done through SPICE simulations using 0.18 µm TSMC CMOS technology parameter. The fractional capacitors of orders 0.2 and 0.5 are realized using truncated infinite order domino RC ladder network and are considered for all simulations in this work. The proposed IIMC is experimentally verified through hardware prototyping using LM 13600N dual OTAs IC. The simulation and experimental results corroborate with theoretical prepositions. PubDate: 2018-10-01 DOI: 10.1007/s10470-018-1315-1 Issue No:Vol. 97, No. 1 (2018)