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 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [7 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2352 journals]
• A power-efficient 14.8-GHz CMOS programmable frequency divider with
quadrature outputs in 40-nm CMOS process
• Authors: Sen Huang; Shengxi Diao; Fujiang Lin
Pages: 189 - 196
Abstract: Abstract This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm2 (114.6 μm × 23.3 μm).
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1037-9
Issue No: Vol. 93, No. 2 (2017)

• A highly efficient class-EF 2 power amplifier in GaAs pHEMT technology
• Authors: A. R. Dehqan; Siroos Toofan; Ali Medi
Pages: 197 - 203
Abstract: Abstract This paper presents a highly efficient class-EF2 power amplifier in GaAs pHEMT technology with high output power. Drain swing voltage of class-E power amplifier (PA) imposes a restriction on its output power. In this work, using a combination of class-E and F relaxes this limitation which may help in increasing DC supply voltage. Higher DC supply voltage of class-EF2 PA leads to increased output power and efficiency, as output power is proportional to supply voltage. In addition, higher supply voltage permits PA to work under lower current which can cause to reduce power dissipation. Proposed class-EF2 PA is implemented in a single recess AlGaAs–InGaAs pHEMT technology with 0.25-µm gate length; power added efficiency of 52% at 31 dBm output power is achieved at 1.8 GHz.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1038-8
Issue No: Vol. 93, No. 2 (2017)

• A 0.1–1.1 GHz inductorless differential LNA with double g m -boosting
and positive feedback
• Authors: Xu Yan; Cen Chen; Lu Yang; Jili Zhang; Fujiang Lin
Pages: 205 - 215
Abstract: Abstract A 0.1–1.1 GHz wideband low-noise amplifier (LNA) is proposed in this paper. The LNA is a fully differential common-gate structure. Large equivalent transconductance $$(g_m)$$ is realized by active $$g_m$$ -boost and capacitive cross-coupling. By introducing a positive feedback path, the circuit increases design freedom. It alleviates the tradeoff between input matching, gain and noise performance. The proposed LNA avoids the use of on-chip inductors to save area and cost. A prototype is implemented in standard TSMC 180-nm CMOS technology. From the measurement, the proposed LNA shows a 19 dB voltage gain with a 1 GHz 3-dB bandwidth. The minimum noise figure (NF) is 3.1 dB. The LNA achieves a return loss greater than 10 dB across the entire band and the third-order input-referred intercept (IIP3) is better than $$-\,2.9$$  dBm. The core consumes 3.8 mW from 1-V supply occupying an area of 0.03  $$\hbox {mm}^2$$ .
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1043-y
Issue No: Vol. 93, No. 2 (2017)

• Design and analysis of a low-noise saw-less receiver front-end resistant
to strong out-of-band blocker
• Authors: Amin Mohammadpour; Abdolreza Nabavi
Pages: 217 - 235
Abstract: Abstract Design and analysis of a SAW-less front-end resistant to strong out-of-band blocker is presented which utilizes a main-path containing an LNA along with a 12.5% mixer and a baseband amplifier. Also, it employs an auxiliary-path using a 12.5% mixer and a baseband amplifier. Multiple N-path filtering technique is employed to improve the NF and gain of the front-end in the presence of strong out-of-band blocker. The linearity of LNA, enhanced by series resistors in the LNA inputs, is analyzed by Volterra series analysis. Using noise cancellation technique on this structure relaxes the concern of series resistor noise contribution. Furthermore, new analyses are given for N-path-switching clock non-idealities, considering overlap and its effect on input matching. Analysis and simulation results, using 0.18 µm CMOS technology, show about 6 and 5 dB improvement in LNA IIP3 and front-end NF, respectively, when series resistor is added to the LNA and the auxiliary-path is ON.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1035-y
Issue No: Vol. 93, No. 2 (2017)

• A segmentation layout guarding technique to mitigate parasitic capacitance
of integrated resistors
• Authors: Zhijun Zhou; Paul Warr
Pages: 237 - 243
Abstract: Abstract Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-0982-7
Issue No: Vol. 93, No. 2 (2017)

• A 700 MHz laser radar receiver realized in 0.18 μm HV-CMOS
• Authors: Mikko Hintikka; Juha Kostamovaara
Pages: 245 - 256
Abstract: Abstract This study presents a CMOS receiver chip realized in 0.18 µm High-Voltage CMOS (HV-CMOS) technology and intended for high precision pulsed time-of-flight laser range finding utilizing high-energy sub-ns laser pulses. The IC chip includes a trans-impedance preamplifier, a post-amplifier and a timing comparator. Timing discrimination is based on leading edge detection and the trailing edge is also discriminated for measuring the width of the pulse. The transimpedance of the channel is 25 kΩ, the uncompensated walk error is 470 ps in the dynamic range of 1:21,000 and the input referred equivalent noise current 450 nA (rms).
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1041-0
Issue No: Vol. 93, No. 2 (2017)

• Low power ring oscillator for IoT applications
• Authors: Rajendra Nayak; Iman Kianpoor; Pydi Ganga Bahubalindruni
Pages: 257 - 263
Abstract: Abstract This paper proposes a low power ring oscillator by combining current starving technique with negative skewed delay approach. This design has shown an improvement of more than 50% in the power delay product compared to the state of the art techniques. Circuit simulations are carried out in standard 65 nm technology. The proposed circuit has shown a robust performance against temperature and voltage variation within 10%. Therefore this circuit can find potential applications in IoT devices and RFID tags operating from 10 MHz to 1 GHz.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1015-2
Issue No: Vol. 93, No. 2 (2017)

• A new hybrid TDC based on GRO-pseudo delay architecture with fractional
code and wide time range detection for divider-less ADPLL
Pages: 265 - 275
Abstract: Abstract This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoMP without requiring complicate calibration.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1032-1
Issue No: Vol. 93, No. 2 (2017)

• An open loop compensation technique for reducing supply sensitivity of CML
ring oscillator
• Authors: Ziqian Wang; Xuefei Bai; Shengxi Diao; Fujiang Lin
Pages: 277 - 285
Abstract: Abstract The causes of supply induced noise are investigated and a circuit technique that reduces the supply sensitivity of CML ring oscillator is presented. This technique applies a current bias circuit with negative supply sensitivity to compensate the intrinsic positive sensitivity of VCO and alleviate the impact of supply voltage fluctuation. A prototype chip is fabricated in a 180 nm CMOS process to prove its rejection of supply noise.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1039-7
Issue No: Vol. 93, No. 2 (2017)

• Analysis and design of low-voltage low-power high-speed double tail
current dynamic latch comparator
• Authors: Vijay Savani; N. M. Devashrayee
Pages: 287 - 298
Abstract: Abstract The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1040-1
Issue No: Vol. 93, No. 2 (2017)

• Analog circuit sizing using local biasing
• Authors: Srdjan Dragomira Djordjevic
Pages: 299 - 308
Abstract: Abstract The analog circuit design approach based on local biasing is shown to be very attractive as it removes the nonlinearity in the biasing procedure. Based on this design approach, we offer a new technique for the sizing of analog integrated circuits. The proposed technique is based on the relations that exist between linear elements of a cut-set or a loop when the voltages and currents in the remaining elements are held fixed. These relations enable the designer to fix a circuit variable (biasing current or voltage of a transistor) in exchange for a set of interrelated element values that can be independently changed. The proposed procedure allows us to directly change the element values or the DC parameter values for the active loads without being concerned about the DC biasing. Therefore, the circuit designer is able to manage tradeoffs in the design by comparing multiple solutions that meet the desired criteria. Moreover, multiple circuit simulations are not necessary in the case when any of the calculated element values is not realistic or workable.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1017-0
Issue No: Vol. 93, No. 2 (2017)

• Linear in dB, sub 0.2 dB gain-step CMOS programmable gain amplifier
for ultrasound applications
• Authors: Yarallah Koolivand; Omid Shoaei; Shahin Jafarabadi-Ashtiani
Pages: 309 - 318
Abstract: Abstract In this paper a new approach for controlling the gain of a programmable gain amplifier (PGA) using an eight-bit digital word has been proposed. Eight stages of R–2R ladder attenuators have been employed for attenuating the input signal. The output of the ladder network feeds the nine gm stages as a part of the PGA. Making use of three MSB bits of the control word, at each instance just the two successive gm stages are active whose tail currents are precisely determined to set the PGA linear gain in dB. A current bank composed of 32 current sources has been used for driving the tail currents of the active gm stages. The current sources that bias the active gm stages are controlled by the five LSB bits of the digital control word. Thanks to the proposed technique, the values of the current sources are determined so that the gain of the circuit is based on a ratio-metric parameter making the circuit less sensitive to process variations. For verification of the proposed idea, a differential PGA is design in a 0.18 µm 1.8 V CMOS technology. The gain of the designed circuit changes from 20.8 to −27.4 dB in 256 steps linearly in dB so that the maximum gain error respect to its ideal value is less than 0.03 dB in different corner cases. At the maximum gain, the bandwidth and the input referred noise voltage of the PGA are 150 MHz and 3.5 nv/√Hz, respectively, while the overall circuit draws 6 mA from a 1.8 V power supply.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1016-1
Issue No: Vol. 93, No. 2 (2017)

• Bio-cellular processes modeling on silicon substrate: receptor–ligand
binding and Michaelis Menten reaction
• Authors: Maria Waqas; Muhammad Khurram; S. M. Rezaul Hasan
Pages: 329 - 340
Abstract: Abstract There has been a growing interest and motivation in analog electronic circuit modeling of bio-cellular networks, which forms the basis of cellular functions of all living organisms. The complexity and size of such networks has made this task arduous, while opening up new opportunities as well. A number of modeling techniques, from mathematical models to computer simulations, have been used in this domain to aid the interpretation of such complex and sophisticated networks. This research article focuses on modeling of bio-cellular structures and processes on silicon substrate using transistors in analog domain. MOS transistor analogies for some very commonly found bio-cellular reactions namely receptor–ligand kinetics and Michaelis Menten kinetics have been presented, which are based on previously established ordinary differential equation representation models of these bio-cellular processes. It has been shown mathematically and through simulations that a number of bio-chemical entities in the kinetic processes map naturally to some electronic entities, and exploiting these similarities can drastically reduce the size of the corresponding silicon mimetics. The suggested circuits use lesser number of transistors than the existing approaches in this domain, while producing the same behavior satisfactorily. This can to some extent ease the development of larger networks with more complex interactions, hence mitigating the intricacy involved in cellular processes when viewed as a complete system and can contribute positively to multiple disciplines like genetics, bio-informatics, medical sciences, and even computer science and engineering.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1044-x
Issue No: Vol. 93, No. 2 (2017)

• Enhancement of noise-suppressed speech by spectral processing implemented
in a digital signal processor
• Authors: Hajer Rahali; Zied Hajaiej
Pages: 341 - 350
Abstract: Abstract This paper presents a noisy suppressed speech enhancement method by combining the basic spectral subtraction technique and spectral processing in the frequency domain to provide better noise suppression as well as better enhancement in the speech regions. In contrast to several previous approaches we do not try to achieve a complete removal of the noise, but instead our goal is to preserve a pre-defined amount of the original noise in the processed signal. This is accomplished by exploiting the masking properties of the human auditory system. The proposed algorithm is named PM “Proposed Method” which simulates properties of the human auditory system and applies it to the speech recognition system to enhance its robustness. The performance of the speech enhancement algorithm using the proposed masking model was compared with three other speech enhancement methods over 4 different noise types and five SNRs. The performances of the proposed approach are objectively and subjectively compared to the conventional approaches to highlight the aforementioned improvement. In this paper we discuss the design and development of a digital signal processor (DSP) implementation to achieve real-time performance of our filter. The target processor is a Texas Instruments TMS320C6713 floating point DSP.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1042-z
Issue No: Vol. 93, No. 2 (2017)

• A novel full-wave rectifier/sinusoidal frequency doubler topology based on
CFOAs
• Authors: Erkan Yuce; Shahram Minaei; Muhammed A. Ibrahim
Pages: 351 - 362
Abstract: Abstract A novel topology for realizing voltage-mode (VM) full-wave rectifier/sinusoidal frequency doubler based on current feedback operational amplifiers (CFOAs) and n-channel metal-oxide semiconductor (NMOS) transistors is proposed in this study. The proposed full-wave rectifier structure employs two CFOAs and three enhancement-mode NMOS transistors. With a slight modification, the sinusoidal frequency doubler circuit can be adopted from the full-wave rectifier circuit by replacing a grounded resistor instead of one of the NMOS transistors. Both of the proposed circuits enjoy low output and high input impedance properties which make them convenient for cascading easily with other VM circuits without needing any extra buffer circuits. No passive component matching conditions are needed. The proposed circuits are simulated by using SPICE program to verify the theoretical analysis.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1033-0
Issue No: Vol. 93, No. 2 (2017)

• Memristor-based approximate matrix multiplier
• Authors: Mohsen Nourazar; Vahid Rashtchi; Ali Azarpeyvand; Farshad Merrikh-Bayat
Pages: 363 - 373
Abstract: Abstract The parallel structure of matrix multipliers makes them fascinating candidates to benefit from memristors’ high density architecture. This paper first explains a memristor-based analog vector–matrix multiplier suitable for approximate computing. According to the existence of fast and efficient converters, namely, DACs and ADCs, in the field of approximate computing and the programmability of memristors, the presented vector–matrix multiplier is combined with digital circuits which it leads to a matrix–matrix multiplier as an extension. In this work, opamps’ characteristics such as power and speed, distribution of matrix elements, and memristors’ faults have been considered and their effects on performance, accuracy, and efficiency of the proposed multiplier have been analyzed. Also, a new structure for handling negative numbers has been proposed. All the circuits have been simulated using “Ngspice mixed-signal circuit simulator” in C++ programming environment. The simulation results revealed that the multiplier’s analog core brought gains in terms of performance and energy when acceptable ranges of inaccuracies in results could be tolerated.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1029-9
Issue No: Vol. 93, No. 2 (2017)

• LSB split capacitor SAR ADC with 99.2% switching energy reduction
• Authors: Behzad Ghanavati; Ebrahim Abiri; Mohammad Reza Salehi; Aida Keyhani; Arindam Sanyal
Pages: 375 - 382
Abstract: Abstract A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.
PubDate: 2017-11-01
DOI: 10.1007/s10470-017-1046-8
Issue No: Vol. 93, No. 2 (2017)

• Contactless hand tremor detector based on an inductive sensor
• Authors: W. Y. Shi; J.-C. Chiao
Abstract: Abstract A contactless detector is presented for evaluating hand tremors caused by exercise-induced fatigue and early Parkinson’s disease. The device consists of a spiral coil, a microcontroller, and an inductive sensor circuitry. Theory shows that the resonant frequency of the circuitry increases when the distance between the hand and the spiral coil decreases, thus small variations of distance from tremor can be detected from the changes of resonant frequencies. A mechanical hand was built for experiments to simulate human hand tremors with repeatability at a fixed frequency. The magnitudes and frequencies of the tremors in the mechanical hand were quantitatively identified using the inductive sensor. Hence, feasibility and accuracy of the contactless hand tremor detector were determined. A triaxial accelerometer was used for comparison. By comparing spectral distributions and magnitudes of the tremors, the inductive sensor performed better than the accelerometer. The detector was applied to evaluate actual hand tremors of three subjects who had undergone exercise to induce tremors. The tremor waveform amplitudes of the subjects were quantitatively analyzed by the standard deviations method. The increased signal energies of exercise-induced tremor within 8–12 Hz were confirmed. Then, a subject with early Parkinson’s disease was evaluated by the proposed hand tremor detector. The tremor magnitudes and frequencies of the patient hand were quantitatively identified within in 4–7 Hz. Therefore, the new contactless hand tremor detector can be developed as a clinical instrument for monitoring the fatigue symptoms of post-exercise and diagnosing the early Parkinson’s disease.
PubDate: 2017-10-11
DOI: 10.1007/s10470-017-1055-7

• Ultra low power beta multiplier-based current reference circuit
• Authors: Shailesh Singh Chouhan; Kari Halonen
Abstract: Abstract This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1–2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V.
PubDate: 2017-10-10
DOI: 10.1007/s10470-017-1057-5

• PSR enhancement techniques for output-capacitor-free LDO regulator design
• Authors: Soyeon Joo; SoYoung Kim
Abstract: Abstract In this paper, power-supply rejection (PSR) enhancement techniques for a output-capacitor-free low drop-out (LDO) regulator with an NMOS pass transistor are presented. For DC PSR and bandwidth enhancement, DC PSR compensation and capacitor cancelation circuits were developed on the basis of precisely derived PSR models of the conventional LDO regulator. The effectiveness of the PSR enhancement techniques were verified using analytic PSR models, SPICE simulation, and measurements. The fabricated LDO regulator using 0.18  $$\upmu$$ m CMOS technology maintains PSR less than $$-74\,\hbox {dB}$$ up to 10 MHz, while delivering the output current and voltage of 25 mA and 1.2 V, respectively.
PubDate: 2017-10-04
DOI: 10.1007/s10470-017-1045-9

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