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  Subjects -> COMPUTER SCIENCE (Total: 1988 journals)
    - ANIMATION AND SIMULATION (29 journals)
    - ARTIFICIAL INTELLIGENCE (99 journals)
    - AUTOMATION AND ROBOTICS (100 journals)
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    - COMPUTER GAMES (16 journals)
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    - COMPUTER SCIENCE (1153 journals)
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    - INFORMATION SYSTEMS (104 journals)
    - INTERNET (92 journals)
    - SOCIAL WEB (50 journals)
    - SOFTWARE (33 journals)
    - THEORY OF COMPUTING (8 journals)

COMPUTER SCIENCE (1153 journals)                  1 2 3 4 5 6 | Last

Showing 1 - 200 of 872 Journals sorted alphabetically
3D Printing and Additive Manufacturing     Full-text available via subscription   (Followers: 14)
Abakós     Open Access   (Followers: 3)
Academy of Information and Management Sciences Journal     Full-text available via subscription   (Followers: 68)
ACM Computing Surveys     Hybrid Journal   (Followers: 22)
ACM Journal on Computing and Cultural Heritage     Hybrid Journal   (Followers: 9)
ACM Journal on Emerging Technologies in Computing Systems     Hybrid Journal   (Followers: 13)
ACM Transactions on Accessible Computing (TACCESS)     Hybrid Journal   (Followers: 3)
ACM Transactions on Algorithms (TALG)     Hybrid Journal   (Followers: 16)
ACM Transactions on Applied Perception (TAP)     Hybrid Journal   (Followers: 6)
ACM Transactions on Architecture and Code Optimization (TACO)     Hybrid Journal   (Followers: 9)
ACM Transactions on Autonomous and Adaptive Systems (TAAS)     Hybrid Journal   (Followers: 7)
ACM Transactions on Computation Theory (TOCT)     Hybrid Journal   (Followers: 11)
ACM Transactions on Computational Logic (TOCL)     Hybrid Journal   (Followers: 4)
ACM Transactions on Computer Systems (TOCS)     Hybrid Journal   (Followers: 18)
ACM Transactions on Computer-Human Interaction     Hybrid Journal   (Followers: 12)
ACM Transactions on Computing Education (TOCE)     Hybrid Journal   (Followers: 3)
ACM Transactions on Design Automation of Electronic Systems (TODAES)     Hybrid Journal   (Followers: 1)
ACM Transactions on Economics and Computation     Hybrid Journal  
ACM Transactions on Embedded Computing Systems (TECS)     Hybrid Journal   (Followers: 4)
ACM Transactions on Information Systems (TOIS)     Hybrid Journal   (Followers: 20)
ACM Transactions on Intelligent Systems and Technology (TIST)     Hybrid Journal   (Followers: 9)
ACM Transactions on Interactive Intelligent Systems (TiiS)     Hybrid Journal   (Followers: 4)
ACM Transactions on Multimedia Computing, Communications, and Applications (TOMCCAP)     Hybrid Journal   (Followers: 10)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)     Hybrid Journal   (Followers: 7)
ACM Transactions on Sensor Networks (TOSN)     Hybrid Journal   (Followers: 8)
ACM Transactions on Speech and Language Processing (TSLP)     Hybrid Journal   (Followers: 11)
ACM Transactions on Storage     Hybrid Journal  
ACS Applied Materials & Interfaces     Full-text available via subscription   (Followers: 21)
Acta Automatica Sinica     Full-text available via subscription   (Followers: 3)
Acta Universitatis Cibiniensis. Technical Series     Open Access  
Ad Hoc Networks     Hybrid Journal   (Followers: 11)
Adaptive Behavior     Hybrid Journal   (Followers: 11)
Advanced Engineering Materials     Hybrid Journal   (Followers: 26)
Advanced Science Letters     Full-text available via subscription   (Followers: 7)
Advances in Adaptive Data Analysis     Hybrid Journal   (Followers: 8)
Advances in Artificial Intelligence     Open Access   (Followers: 16)
Advances in Calculus of Variations     Hybrid Journal   (Followers: 2)
Advances in Catalysis     Full-text available via subscription   (Followers: 5)
Advances in Computational Mathematics     Hybrid Journal   (Followers: 15)
Advances in Computer Science : an International Journal     Open Access   (Followers: 13)
Advances in Computing     Open Access   (Followers: 2)
Advances in Data Analysis and Classification     Hybrid Journal   (Followers: 54)
Advances in Engineering Software     Hybrid Journal   (Followers: 25)
Advances in Geosciences (ADGEO)     Open Access   (Followers: 10)
Advances in Human Factors/Ergonomics     Full-text available via subscription   (Followers: 25)
Advances in Human-Computer Interaction     Open Access   (Followers: 20)
Advances in Materials Sciences     Open Access   (Followers: 16)
Advances in Operations Research     Open Access   (Followers: 11)
Advances in Parallel Computing     Full-text available via subscription   (Followers: 7)
Advances in Porous Media     Full-text available via subscription   (Followers: 4)
Advances in Remote Sensing     Open Access   (Followers: 37)
Advances in Science and Research (ASR)     Open Access   (Followers: 6)
Advances in Technology Innovation     Open Access   (Followers: 1)
AEU - International Journal of Electronics and Communications     Hybrid Journal   (Followers: 8)
African Journal of Information and Communication     Open Access   (Followers: 6)
African Journal of Mathematics and Computer Science Research     Open Access   (Followers: 4)
Air, Soil & Water Research     Open Access   (Followers: 7)
AIS Transactions on Human-Computer Interaction     Open Access   (Followers: 6)
Algebras and Representation Theory     Hybrid Journal   (Followers: 1)
Algorithms     Open Access   (Followers: 11)
American Journal of Computational and Applied Mathematics     Open Access   (Followers: 4)
American Journal of Computational Mathematics     Open Access   (Followers: 4)
American Journal of Information Systems     Open Access   (Followers: 7)
American Journal of Sensor Technology     Open Access   (Followers: 2)
Anais da Academia Brasileira de Ciências     Open Access   (Followers: 2)
Analog Integrated Circuits and Signal Processing     Hybrid Journal   (Followers: 5)
Analysis in Theory and Applications     Hybrid Journal   (Followers: 1)
Animation Practice, Process & Production     Hybrid Journal   (Followers: 5)
Annals of Combinatorics     Hybrid Journal   (Followers: 3)
Annals of Data Science     Hybrid Journal   (Followers: 9)
Annals of Mathematics and Artificial Intelligence     Hybrid Journal   (Followers: 6)
Annals of Pure and Applied Logic     Open Access   (Followers: 2)
Annals of Software Engineering     Hybrid Journal   (Followers: 12)
Annual Reviews in Control     Hybrid Journal   (Followers: 6)
Anuario Americanista Europeo     Open Access  
Applicable Algebra in Engineering, Communication and Computing     Hybrid Journal   (Followers: 2)
Applied and Computational Harmonic Analysis     Full-text available via subscription   (Followers: 2)
Applied Artificial Intelligence: An International Journal     Hybrid Journal   (Followers: 14)
Applied Categorical Structures     Hybrid Journal   (Followers: 2)
Applied Clinical Informatics     Hybrid Journal   (Followers: 2)
Applied Computational Intelligence and Soft Computing     Open Access   (Followers: 12)
Applied Computer Systems     Open Access   (Followers: 1)
Applied Informatics     Open Access  
Applied Mathematics and Computation     Hybrid Journal   (Followers: 32)
Applied Medical Informatics     Open Access   (Followers: 10)
Applied Numerical Mathematics     Hybrid Journal   (Followers: 5)
Applied Soft Computing     Hybrid Journal   (Followers: 16)
Applied Spatial Analysis and Policy     Hybrid Journal   (Followers: 4)
Architectural Theory Review     Hybrid Journal   (Followers: 3)
Archive of Applied Mechanics     Hybrid Journal   (Followers: 4)
Archive of Numerical Software     Open Access  
Archives and Museum Informatics     Hybrid Journal   (Followers: 120)
Archives of Computational Methods in Engineering     Hybrid Journal   (Followers: 4)
Artifact     Hybrid Journal   (Followers: 2)
Artificial Life     Hybrid Journal   (Followers: 6)
Asia Pacific Journal on Computational Engineering     Open Access  
Asia-Pacific Journal of Information Technology and Multimedia     Open Access   (Followers: 1)
Asian Journal of Computer Science and Information Technology     Open Access  
Asian Journal of Control     Hybrid Journal  
Assembly Automation     Hybrid Journal   (Followers: 2)
at - Automatisierungstechnik     Hybrid Journal   (Followers: 1)
Australian Educational Computing     Open Access  
Automatic Control and Computer Sciences     Hybrid Journal   (Followers: 3)
Automatic Documentation and Mathematical Linguistics     Hybrid Journal   (Followers: 5)
Automatica     Hybrid Journal   (Followers: 9)
Automation in Construction     Hybrid Journal   (Followers: 6)
Autonomous Mental Development, IEEE Transactions on     Hybrid Journal   (Followers: 8)
Basin Research     Hybrid Journal   (Followers: 5)
Behaviour & Information Technology     Hybrid Journal   (Followers: 52)
Bioinformatics     Hybrid Journal   (Followers: 246)
Biomedical Engineering     Hybrid Journal   (Followers: 16)
Biomedical Engineering and Computational Biology     Open Access   (Followers: 13)
Biomedical Engineering, IEEE Reviews in     Full-text available via subscription   (Followers: 17)
Biomedical Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 32)
Briefings in Bioinformatics     Hybrid Journal   (Followers: 45)
British Journal of Educational Technology     Hybrid Journal   (Followers: 125)
Broadcasting, IEEE Transactions on     Hybrid Journal   (Followers: 10)
c't Magazin fuer Computertechnik     Full-text available via subscription   (Followers: 2)
CALCOLO     Hybrid Journal  
Calphad     Hybrid Journal  
Canadian Journal of Electrical and Computer Engineering     Full-text available via subscription   (Followers: 14)
Catalysis in Industry     Hybrid Journal   (Followers: 1)
CEAS Space Journal     Hybrid Journal  
Cell Communication and Signaling     Open Access   (Followers: 1)
Central European Journal of Computer Science     Hybrid Journal   (Followers: 5)
CERN IdeaSquare Journal of Experimental Innovation     Open Access  
Chaos, Solitons & Fractals     Hybrid Journal   (Followers: 3)
Chemometrics and Intelligent Laboratory Systems     Hybrid Journal   (Followers: 15)
ChemSusChem     Hybrid Journal   (Followers: 7)
China Communications     Full-text available via subscription   (Followers: 7)
Chinese Journal of Catalysis     Full-text available via subscription   (Followers: 2)
CIN Computers Informatics Nursing     Full-text available via subscription   (Followers: 12)
Circuits and Systems     Open Access   (Followers: 16)
Clean Air Journal     Full-text available via subscription   (Followers: 2)
CLEI Electronic Journal     Open Access  
Clin-Alert     Hybrid Journal   (Followers: 1)
Cluster Computing     Hybrid Journal   (Followers: 1)
Cognitive Computation     Hybrid Journal   (Followers: 4)
COMBINATORICA     Hybrid Journal  
Combustion Theory and Modelling     Hybrid Journal   (Followers: 13)
Communication Methods and Measures     Hybrid Journal   (Followers: 11)
Communication Theory     Hybrid Journal   (Followers: 19)
Communications Engineer     Hybrid Journal   (Followers: 1)
Communications in Algebra     Hybrid Journal   (Followers: 3)
Communications in Partial Differential Equations     Hybrid Journal   (Followers: 3)
Communications of the ACM     Full-text available via subscription   (Followers: 53)
Communications of the Association for Information Systems     Open Access   (Followers: 18)
COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering     Hybrid Journal   (Followers: 3)
Complex & Intelligent Systems     Open Access  
Complex Adaptive Systems Modeling     Open Access  
Complex Analysis and Operator Theory     Hybrid Journal   (Followers: 2)
Complexity     Hybrid Journal   (Followers: 6)
Complexus     Full-text available via subscription  
Composite Materials Series     Full-text available via subscription   (Followers: 9)
Computación y Sistemas     Open Access  
Computation     Open Access  
Computational and Applied Mathematics     Hybrid Journal   (Followers: 2)
Computational and Mathematical Methods in Medicine     Open Access   (Followers: 2)
Computational and Mathematical Organization Theory     Hybrid Journal   (Followers: 2)
Computational and Structural Biotechnology Journal     Open Access   (Followers: 2)
Computational and Theoretical Chemistry     Hybrid Journal   (Followers: 9)
Computational Astrophysics and Cosmology     Open Access   (Followers: 1)
Computational Biology and Chemistry     Hybrid Journal   (Followers: 12)
Computational Chemistry     Open Access   (Followers: 2)
Computational Cognitive Science     Open Access   (Followers: 2)
Computational Complexity     Hybrid Journal   (Followers: 4)
Computational Condensed Matter     Open Access  
Computational Ecology and Software     Open Access   (Followers: 8)
Computational Economics     Hybrid Journal   (Followers: 9)
Computational Geosciences     Hybrid Journal   (Followers: 14)
Computational Linguistics     Open Access   (Followers: 23)
Computational Management Science     Hybrid Journal  
Computational Mathematics and Modeling     Hybrid Journal   (Followers: 8)
Computational Mechanics     Hybrid Journal   (Followers: 4)
Computational Methods and Function Theory     Hybrid Journal  
Computational Molecular Bioscience     Open Access   (Followers: 2)
Computational Optimization and Applications     Hybrid Journal   (Followers: 7)
Computational Particle Mechanics     Hybrid Journal   (Followers: 1)
Computational Research     Open Access   (Followers: 1)
Computational Science and Discovery     Full-text available via subscription   (Followers: 2)
Computational Science and Techniques     Open Access  
Computational Statistics     Hybrid Journal   (Followers: 13)
Computational Statistics & Data Analysis     Hybrid Journal   (Followers: 29)
Computer     Full-text available via subscription   (Followers: 84)
Computer Aided Surgery     Hybrid Journal   (Followers: 3)
Computer Applications in Engineering Education     Hybrid Journal   (Followers: 6)
Computer Communications     Hybrid Journal   (Followers: 10)
Computer Engineering and Applications Journal     Open Access   (Followers: 5)
Computer Journal     Hybrid Journal   (Followers: 7)
Computer Methods in Applied Mechanics and Engineering     Hybrid Journal   (Followers: 22)
Computer Methods in Biomechanics and Biomedical Engineering     Hybrid Journal   (Followers: 10)
Computer Methods in the Geosciences     Full-text available via subscription   (Followers: 1)
Computer Music Journal     Hybrid Journal   (Followers: 14)
Computer Physics Communications     Hybrid Journal   (Followers: 6)
Computer Science - Research and Development     Hybrid Journal   (Followers: 7)
Computer Science and Engineering     Open Access   (Followers: 17)
Computer Science and Information Technology     Open Access   (Followers: 11)
Computer Science Education     Hybrid Journal   (Followers: 12)
Computer Science Journal     Open Access   (Followers: 20)
Computer Science Master Research     Open Access   (Followers: 10)

        1 2 3 4 5 6 | Last

Journal Cover Analog Integrated Circuits and Signal Processing
  [SJR: 0.21]   [H-I: 37]   [5 followers]  Follow
    
   Hybrid Journal Hybrid journal (It can contain Open Access articles)
   ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030
   Published by Springer-Verlag Homepage  [2353 journals]
  • A hybrid DAC switching technique for SAR ADCs
    • Authors: Sharath R. Srinivasan; Poras T. Balsara
      Pages: 179 - 187
      Abstract: Abstract In recent years, the area of Wireless Sensor Networks has seen a tremendous growth and is instrumental in a multitude of applications ranging from health monitoring to geo fencing. Analog-to-Digital Converters (ADCs) are vital to any low-cost, energy-efficient sensor node in that they convert the sensed signal into its digital counterpart, which is then used processed by the digital circuitry. In this paper, a Capacitive Digital-to-Analog Converter (CDAC) switching technique is proposed that is aimed toward the design of an energy-efficient ADC. The presented switching technique is \(97.85\%\) more energy-efficient than the traditional CDAC architecture. Besides its energy efficiency, the technique reduces the overall size of the CDAC and its settling time. Theoretical analysis has been presented along with detailed simulation results as a proof of concept.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0974-7
      Issue No: Vol. 92, No. 2 (2017)
       
  • Noise shaping Riemann: an energy efficient data conversion scheme
    • Authors: Yoan Veyrac; Francois Rivet; Yann Deval
      Pages: 189 - 197
      Abstract: Abstract This paper presents a novel conversion scheme for time signals, especially suited for wireless communication applications. The digital/analog data representation paradigm is discussed and critical aspects are determined. It involves digital information coding, two-way digital/analog conversion and their respective efficiency. The proposed conversion scheme relies on a slight oversampling ratio (OSR), combined with a differentiating coding and a \(1^\mathrm{st}\) order noise shaping loop. It achieves a resolution increased by 2.5 effective number of bits per doubling of the OSR. The resulting conversion efficiency combined with a moderate digital coding complexity leads to a substantial improvement of the energy cost of conversion compared to conventional Nyquist rate architectures. The efficiency gain is even higher for converters limited by thermal noise. It can reach a ten fold improvement for OSR around 10, which makes this architecture a good option for the handling of radio frequency signals.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0980-9
      Issue No: Vol. 92, No. 2 (2017)
       
  • Design and analysis of high-speed split-segmented switched-capacitor DACs
    • Authors: Quoc-Tai Duong; Ameya Bhide; Atila Alvandpour
      Pages: 199 - 217
      Abstract: Abstract In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area W–C u is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, C u ) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0981-8
      Issue No: Vol. 92, No. 2 (2017)
       
  • A simple circuit technique to relax the feedback timing of ΔΣ ADC for
           high-speed and high-accuracy applications
    • Authors: Youngho Jung; Gabor C. Temes
      Pages: 219 - 223
      Abstract: Abstract A novel and simple circuit technique to relax the feedback timing of input feed-forward ΔΣ analog-to-digital converter (ADC) is proposed for wideband and high-accuracy applications. The proposed method allows the use of low-speed comparator and DEM logic even for high-speed operation which helps to reduce the power consumption. A delta-sigma ADC with relaxed feedback timing was designed and simulated. The results verify the advantages of the proposed technique.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0993-4
      Issue No: Vol. 92, No. 2 (2017)
       
  • Design and analysis of low-power and area efficient N-bit parallel binary
           comparator
    • Authors: Chang Chua; R. B. N. Kumar; B. Sireesha
      Pages: 225 - 231
      Abstract: Abstract This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR–NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180nm—technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto \(25\%\) , area (number of transistors) reduces upto \(36\%\) and improves the delay performance \(27\%\) compared to existing technique.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0996-1
      Issue No: Vol. 92, No. 2 (2017)
       
  • A 500 MHz low offset fully differential latched comparator
    • Authors: Saeed Naghavi; Niloofar Sharifi; Mozhdeh Nematzadeh; Tohid Moradi Khanshan; Adib Abrishamifar; Zia Daei Kuzekanani; Jafar Sobhi
      Pages: 233 - 245
      Abstract: Abstract A fully differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a positive feedback or latch stage and the offset cancellation circuitry. The effect of kick-back noise can be significantly reduced by using a pre-amplifier stage. Also, the offset and noise of the latch and offset cancellation stages are attenuated by the gain of the pre-amplifier when referred to the input. Latches regenerate faster than pre-amplifiers and provide a full swing digital output for the comparator. The last stage is the offset cancellation circuitry. The main advantage of the proposed offset cancellation technique is that it does not need to make any interrupt in normal operation of comparator to eliminate offset error. As a result, higher speeds for the comparator can be achieved. Moreover, the power consumption of the proposed offset cancellation circuitry is negligible compared to the overall power consumption. In order to evaluate the performance of the comparator, simulations are performed in a 0.18 μm standard CMOS technology. Simulation results show that the offset values of the pre-amplifier and latch stages are significantly eliminated by this cancellation technique and only about 450 μV offset voltage will be referred to the input due to offset error of the offset cancellation circuitry. The proposed comparator operates at 500 MHz clock frequency and dissipates 373 μW from a 1.8 supply. Also, it has a propagation delay of 138 ps and kick-back noise of 0.54 mV.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0998-z
      Issue No: Vol. 92, No. 2 (2017)
       
  • Mitigating the thermally induced single event crosstalk
    • Authors: Selahattin Sayil; Pankaj Bhowmik
      Pages: 247 - 253
      Abstract: Abstract With advances in technology scaling, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. With scaling, interconnects are also being laid closer to each other causing increased cross-coupling noise effects. Due to strong coupling among wires, SE transients can easily contaminate electronically unrelated circuit paths via SE crosstalk noise effects increasing SE susceptibility of CMOS circuits. This work reports that varying temperature profiles on nearby interconnects can further alleviate SE crosstalk noise effects. The increased temperature affects both interconnect resistance and driving strength of transistors. If temperature induced effects are not properly considered, standard measures taken such as driver sizing may fail causing a new reliability issue. This work first discusses these effects and then proposes a mitigation method for thermally induced SE crosstalk based on adaptive body biasing of driver transistors and a temperature sensor. Simulation results demonstrate that, the proposed method can successfully mitigate thermally induced crosstalk noise by 86% on average.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0992-5
      Issue No: Vol. 92, No. 2 (2017)
       
  • A new NLEO based technique for the detection of burst–suppression
           patterns in multichannel neonatal EEG signals
    • Authors: Parisa Mirzaei; Ghasem Azemi
      Pages: 255 - 262
      Abstract: Abstract In this paper, we propose a new method, based on the nonlinear energy operator (NLEO), to automatically detect burst–suppression (B–S) patterns in multichannel newborn electroencephalograms (EEGs). The proposed approach consists of two algorithms: (1) per-brain region B–S detection and (2) global B–S detection. At first, B–S patterns are detected in each channel using NLEO. Average of NLEO values obtained for all the channels is then calculated to detect the presence of B–S patterns in each brain region. After local B–S detection, the global B–S detection algorithm classifies a sample-point as burst if most of regions are bursting. Otherwise, the sample-point is classified as suppression. The proposed method is validated using a database composed of multichannel EEG signals acquired from 6 neonates. The experimental results show that the proposed approach can detect bursts which occur locally and classify global B–S patterns with a very high accuracy of 98%.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0989-0
      Issue No: Vol. 92, No. 2 (2017)
       
  • ZigBee-based indoor localization system with the personal dynamic
           positioning method and modified particle filter estimation
    • Authors: Mahmut Aykaç; Ergun Erçelebi; Noor Baha Aldin
      Pages: 263 - 279
      Abstract: Abstract We introduce a portable Wireless Sensor Network; which characterized by its great precision, fast detection, real time-monitoring and cheapness. The received signal strength indication (RSSI) is used for estimating the location of the target based on the trilateration algorithm. One of the biggest issues when acquiring a precise location is the numerous calculations that are required within particle filtering. Therefore, we have suggested a modified particle filtering (MPF) using a ZigBee model; in order to minimize both error and huge computations within the indoor environment based on the variance and gradient data-resampling. Increasing the particle weight near the estimated position using RSSI localization helps in avoiding undesired estimations. The MPF algorithm has been enhanced to predict a moving target within an indoor location with an average accuracy of approximately 1.5–2 m while consuming less power. The efficient number of particles has been improved, in addition to the estimated error; in comparison to the classical methods. The results prove that our algorithm can effectively meet the general indoor environmental demands with significant improvements over other algorithms and good position’s evaluation.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0969-4
      Issue No: Vol. 92, No. 2 (2017)
       
  • Minimum energy point tracking based on adaptive voltage scaling circuit
    • Authors: Dongjun Wang; Ping Luo; Yi Bao; Shaowei Zhen; Yajuan He
      Pages: 281 - 291
      Abstract: Abstract In order to realize the low-voltage and low-power dissipation designing of digital circuits, minimum energy point tracking (MEPT) based on adaptive voltage scaling (AVS) circuit is proposed in this paper. With process, voltage and temperature and frequency variance, the supply voltage of digital circuits is decreased dramatically by AVS, and equals to minimum voltage point (MVP), and advantageously in reducing dynamic energy consumption. Based on the MVP, in order to effectively decrease energy consumption of digital circuits, minimum energy point (MEP) of digital circuits is searched via comparing energy dissipation under different supply voltage by MEPT. Therefore, the supply voltage and energy consumption of digital circuits are decreased dramatically by the proposed novel circuit. The proposed circuit has been implemented and fabricated in a standard 0.18 μm CMOS process. The experimental results show that, when operating frequency of load keeps 1.319 MHz, the MVP and MEP of load are 425 and 450 mV, respectively. For operation frequency 5.334 MHz, the MEP changes from 625 to 550 mV with the degree of activity of load difference. Comparing with the traditional fixed voltage circuits, the maximum saving 91% of dynamic energy is realized by the proposed circuit.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0986-3
      Issue No: Vol. 92, No. 2 (2017)
       
  • A low load- and cross-regulation SIDO converter using an adaptive current
           
    • Authors: Young-Ho Jung; Seong-Kwan Hong; Oh-Kyong Kwon
      Pages: 293 - 301
      Abstract: Abstract In this paper, a single-inductor dual-output (SIDO) converter is proposed to generate stable output voltages with low load- and cross-regulations for mobile applications. The proposed converter, which operates in the buck–boost or boost mode, employs an adaptive current sensor and a low-dropout regulator with a selectable charge pump to achieve low load- and cross-regulations. In addition, an error amplifier and comparators are implemented to provide stable dual output voltages of 1.8 and 3.3 V at an input voltage range of between 1.0 and 3.2 V. The proposed SIDO converter was fabricated using a 0.18-μm CMOS process technology and occupies a chip area of 1568 μm × 728 μm. The measurement results show that the maximum power efficiency, load-regulation, and cross-regulation are 89.2%, 0.120 and 0.088 mV/mA, respectively, when the load current changes from 10 to 50 mA.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0990-7
      Issue No: Vol. 92, No. 2 (2017)
       
  • SDTSPC-technique for low power noise aware 1-bit full adder
    • Authors: Preeti Verma; Ajay K. Sharma; Arti Noor; Vinay S. Pandey
      Pages: 303 - 314
      Abstract: Abstract This paper presents a new design named as SDTSPC (Stacked and diode transistor based TSPC) logic for 1-bit full adder to achieve low power noise aware design. Gated transistors are used as stacked transistors from supply to ground path in both sum and carry circuits. One diode connected transistor is placed in series with evaluation transistor to achieve further improved performance in terms of reduced bouncing noise. Analysis is done for power consumption and propagation delay during active and idle mode of operation for both low (25 °C) and high (110 °C) die temperature. Comparing SDTSPC with recently proposed static 1-bit hybrid full adder we get more than 90% improvement in PDP while 30.7% improvement when compared to dynamic TSPC based 1-bit full adder. Corner analysis verifies that our design has the least effect of process exaggeration on PDP and with varying temperature and supply voltage this design keeps lowest value of current among other techniques. SDTSPC design has reduced ground and supply bounce noise. The proposed design is also compared with several previously proposed designs and it is found to have best power delay product (PDP). Further, SDTSPC technique is implemented on 32-bit ripple carry adder as an prolongation of technique.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0994-3
      Issue No: Vol. 92, No. 2 (2017)
       
  • A novel 9T SRAM architecture for low leakage and high performance
    • Authors: Rohit Lorenzo; Saurabh Chaudhury
      Pages: 315 - 325
      Abstract: Abstract A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design metrics. The main objective of the proposed architecture is to minimize the leakage current in an SRAM cell while improving the stability and reducing the read/write delays. The above design metrics of the circuit are compared with the conventional 6T, LP10T and WRE8T SRAM cells under process and temperature variations. It is observed that as compared to conventional SRAM, the proposed 9T SRAM architecture (8 × 16 arrays) reduces static power consumption by 98%, improves the read and write stability by 66.07 and 10.51% respectively. Again, the write delay is reduced to about 95% while read delay is minimized to about 64.1% under different body-bias voltages.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0997-0
      Issue No: Vol. 92, No. 2 (2017)
       
  • Sorting-free digital median filter for SOCs
    • Authors: Saleh Abdel-hafeez; Behrooz Parhami; Arwa Damir
      Pages: 327 - 339
      Abstract: Abstract In this work, we propose a new median-finding algorithm which computes the median value in an input list of integers on-the-fly, without any data-sorting operations. We present a complete digital CMOS implementation, associated timing diagrams, and a formal mathematical proof, which show the overall average number of clock cycles for median-finding to be linearly proportional to the input length, that is, O(N) average-time complexity, when N is less than about 100. Hence, our proposed sorting-free median algorithm is suitable for practical applications on 3 × 3 and 5 × 5 image scan matrices, which are in common use for hand-held devices and entertainment graphics applications. Our proposed hardware precludes the need for SRAM memory or complex circuitry, such as pipelining structures, but rather uses simple registers to hold the input values, performing comparison-swapping on 3 values, along with counting, to derive the median value. There is no restriction on the input sequence with regard to having repeated elements. We evaluate an ASIC design of our sorting-free median algorithm using 90 nm TSMC technology, with 1 V supply voltage and a clock frequency of 2 GHz, on example cases of 3 × 3 (9 values) and 5 × 5 (25 values) image-scan matrices. The resulting designs have a minimum transistor-count ranging from 3202 to 5203. Results show that our sorting-free median algorithm, when used on 512 × 512 images with 8-bit pixels, takes 0.364 and 1.394 ms to scan the complete image using 3 × 3 and 5 × 5 scan matrices, respectively, with the associated power consumption ranging from 3.24 to 1.66 mW.
      PubDate: 2017-08-01
      DOI: 10.1007/s10470-017-0991-6
      Issue No: Vol. 92, No. 2 (2017)
       
  • Low leakage and high CMRR CMOS differential amplifier for biomedical
           application
    • Authors: Prateek Jain; Amit Mahesh Joshi
      Abstract: Abstract A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDD to VOUT or from VSS to VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDD to VSS directly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.
      PubDate: 2017-07-31
      DOI: 10.1007/s10470-017-1027-y
       
  • Fully digital fast transient phase-locked digital LDO-embedded-MDLL for
           DVFS applications
    • Authors: Muhammad Abrar Akram; In-Chul Hwang
      Abstract: Abstract This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (FREF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm2. At the typical VIN = 1.2 V and FREF = 37.4 MHz, the regulated range of voltage was measured to be 0.56–1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than −116 and −104 dBc/Hz, respectively, both at 1 MHz offset.
      PubDate: 2017-07-29
      DOI: 10.1007/s10470-017-1028-x
       
  • A New Method Modifying Single Miller Feedforward Frequency Compensation to
           Drive Large Capacitive Loads: Putting an Attenuator in the Path
    • Authors: Iman Chaharmahali; Shahrooz Asadi; Behnam Dorostkar; Mosa malaknezhad bosra; Mohammad Abedini
      Abstract: Abstract A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.
      PubDate: 2017-07-25
      DOI: 10.1007/s10470-017-1026-z
       
  • A multi-band low noise amplifier with strong immunity to interferers
    • Authors: Zaira Zahir; Gaurab Banerjee; Mohamad A. Zeidan; Jacob A. Abraham
      Abstract: Abstract A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable \(\pi\) network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point ( \(IIP_3\) ) ranges from −15 to 0 dBm. Implemented in a 0.13  \(\upmu\) m CMOS technology, the LNA occupies an active area of about 0.29 mm \(^2\) . This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.
      PubDate: 2017-07-20
      DOI: 10.1007/s10470-017-1020-5
       
  • Bulk-driven class AB fully-balanced differential difference amplifier
    • Authors: Fabian Khateb; Spyridon Vlassis; Tomasz Kulej; George Souliotis
      Abstract: Abstract This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.
      PubDate: 2017-07-17
      DOI: 10.1007/s10470-017-1024-1
       
  • Low power VLSI architecture design of BMC, BPSC and PC schemes
    • Authors: G. Rajakumar; A. Andrew Roobert; T. S. Arun Samuel; D. Gracia Nirmala Rani
      Abstract: Abstract Line coding is used to tune the wave form based on the properties of the physical channel. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. The first objective of the proposed work is to design Generation and Degeneration operations of BMC, BPSC and PC techniques in a single chip. The second objective is to reduce the area and power consumption, by modifying the number of MOS devices used to design the system and by adjusting the width of the MOS devices. The proposed system is designed with 59 transistors and simulated using Cadence® 90 nm technology. This occupies 1290 µm2. Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data has equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.
      PubDate: 2017-07-17
      DOI: 10.1007/s10470-017-1025-0
       
 
 
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