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 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [5 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2345 journals]
• A MOS translinear cell-based configurable block for current-mode analog
signal processing
Pages: 1 - 13
Abstract: This paper, proposes a low-voltage/power, high-speed configurable analog block (CAB) for current-mode nonlinear computation. A novel MOS translinear cell (MTC), two local switch networks and PMOS-NMOS arrays are the basic building blocks of the proposed CAB. This MTC consists of two overlapped translinear loops using the MOS transistors operating in weak inversion region. The proposed CAB is capable to implement such current-mode analog computational processors as one- and four-quadrant multipliers, one- and two-quadrant dividers, squarer, full-wave rectifier (absolute-value), RMS to DC converter and much other. Post-layout plus Monte Carlo simulations of the proposed design with 0.18 µm (level-49 parameters) TSMC technology is performed that prove its superiority over some other advanced works and robustness against process, voltage and temperature variations. This superb feature plus many others, mostly, are due to the precise multilateral analysis and optimal compensate of mismatches and second order effects of the proposed circuit that led to proper selection of devices sizes and deliberate arrangement of the layout.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0959-6
Issue No: Vol. 92, No. 1 (2017)

• Generation of square and triangular wave with independently controllable
frequency and amplitude using OTAs only and its application in PWM
• Authors: Rajeev Kumar Ranjan; Kaushik Mazumdar; Ratnadeep Pal; Satish Chandra
Pages: 15 - 27
Abstract: This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0971-x
Issue No: Vol. 92, No. 1 (2017)

• A high linearity current-controlled CMOS relaxation oscillator with
frequency self-calibration technique
• Authors: Yangyang Lu; Jing Zhu; Yunwu Zhang; Weifeng Sun; Kuo Yu; Jian Chen
Pages: 29 - 37
Abstract: A complementary metal oxide semiconductor relaxation oscillator adopting a new frequency self-calibration technique (FSCT) to improve the linearity is proposed in this paper. The FSCT can detect the peak voltage of the timing capacitor when start-up and change the reference voltage adaptively. Then, the non-linearity of the oscillator caused by the delay of the control circuit and the offset voltage of the comparator can be reduced obviously. The proposed relaxation oscillator with typical frequency of 5 MHz is implemented in 0.5 μm Silicon-On-Insulator Bipolar-CMOS-DMOS process. Measured results show that <0.79% non-linearity in the current–frequency transfer function from 0.1 to 10 MHz without trimming.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0973-8
Issue No: Vol. 92, No. 1 (2017)

• A novel pulse swallow based frequency divider circuit for a phase-locked
loops
• Authors: Manas Kumar Hati; Tarun K. Bhattacharyya
Pages: 55 - 69
Abstract: A new and unique frequency divider circuit has been proposed for this work. In this paper, we have implemented a $$\varDelta \varSigma$$ fractional-N PLL using a proposed pulse swallow based frequency divider and a programmable prescaler divider circuit. Advantages of the proposed pulse swallow based frequency divider circuit have been illustrated and its usefulness are described in details. This novel pulse swallow based frequency divider technique does not include any reset or reload signal for the swallow counter as it is normally triggered by the SR latch output signal in conventional pulse swallow based frequency divider circuit. Insertion of a variable delay element at the output of the program counter can be eliminated which is normally used to settle the problem of arrival of the falling edge of the swallow counter pulse. In addition, preset enable signal can be generated without any frequency dependent delay generation block and in few cases without selection of any frequency dependent RC network block. The residual phase noise output of the divider at 1 MHz offset frequency is $$-174.5$$  dBc/Hz for a carrier signal frequency of 4.7 GHz and power consumption is 9 mW from a 1.2 V power supply. The design of the fractional-N PLL has been carried out in 130 nm standard CMOS process. There is no zero division in the proposed frequency divider’s swallow counter for any counting state due to the novel mathematical calculating algorithm for the pulse swallow divider circuit.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0979-2
Issue No: Vol. 92, No. 1 (2017)

• Highly stable analog front-end design for NFC smart card
• Authors: Trio Adiono; Amy Hamidah Salman; Yusuf Purna Yudhanto; Nur Ahmadi; Suksmandhira Harimurti
Pages: 71 - 79
Abstract: In order to increase user experience in using near field communication smartcard, analog front-end (AFE) module is required to provide a sufficient and a well-regulated voltage regardless the distance between the card and the reader. A highly stable AFE design for energy harvesting purpose is introduced in this paper. The design consists of antenna, rectifier, voltage limiter, bandgap reference, and low-dropout (LDO) voltage regulator circuit. The antenna is designed to resonate at 13.56 MHz as regulated by ISO/IEC 14443-2. In order to simplify the implementation using 0.18 μm CMOS process, a full-wave rectifier circuit is built of all low-threshold-voltage diode-connected PMOS transistors. To protect the system from undesired excessive input voltages, a voltage limiter circuit is included in the module. Moreover, control and maintain a stable supply voltage for the whole system, a robust LDO voltage regulator and bandgap circuits are specially designed for this purpose. The LDO is able to provide a stable 1.8 V of supply voltage with a sub-1% ripple factor even under a low input current as low as 20 mA.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0978-3
Issue No: Vol. 92, No. 1 (2017)

• Dual-time resolution time-based transceiver for low-power serial
interfaces
• Authors: Mostafa Rashdan
Pages: 81 - 89
Abstract: A dual-time resolution differential-time signaling (DTR-DTS) architecture is proposed in this paper. The number of transmitted bits per symbol in a time-based serial link can be increased by using dual-time resolution pulse-position modulation at the transmitter side instead of using the conventional pulse-position modulation without significantly affecting the transmitted signal bandwidth. Using the proposed architecture, the receiver design is simplified by using time-to-digital converter (TDC) circuits with less number of bits compared to the differential-time signaling (DTS) architecture for the same link rate. The design details are presented in this paper. A simulated 8-bit 12 Gb/s DR-DTS link has been designed in 65 nm mixed signal CMOS process using Cadence tools. Four TDC circuits, 2-bits each, have been used to recover the 8-bits from the received signal. The simulated DTR-DTS link consumes 3.6 mW without the driver circuit.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0977-4
Issue No: Vol. 92, No. 1 (2017)

• Asymmetrically CPW-fed ladder-shaped fractal antenna for UWB applications
• Authors: Sarthak Singhal; Amit Kumar Singh
Pages: 91 - 101
Abstract: A compact asymmetrically CPW-fed ladder- shaped UWB fractal antenna is presented. An impedance bandwidth of 4.56–13.1 GHz is achieved by using four iterations of H-shaped radiating element, modified feed line, asymmetrical feeding and slot loaded ground plane. Omnidirectional radiation patterns are achieved in H-plane at all frequency points in the operating frequency band. The bidirectional nature of E-plane patterns at lower frequencies is observed to be shifted to directional nature at higher frequencies. The designed antenna structure has an average gain of 2.84 dB with a constant group delay. The designed antenna structure is analyzed for three different substrate materials i.e. CNT, Ni0.2Co0.2Zn0.6Fe2O4 and FR-4 epoxy. A good agreement is achieved between the simulated and measured results. This antenna structure has advantages of wider bandwidth and smaller dimensions over already reported ones.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0976-5
Issue No: Vol. 92, No. 1 (2017)

• RF transceiver and transmission line behavioral modeling in VHDL-AMS for
wired RFNoC
• Authors: Lounis Zerioul; Myriam Ariaudo; Emmanuelle Bourdel
Pages: 103 - 114
Abstract: Despite the exceptional progress of MPSoC architectures, on chip communication networks remain a lock for the evolution of their performances due to the power consumption and the delay in data carrying. In this context, the wired radio frequency (RF) network on chip (RFNoC) has emerged. In this paper, we developed a library of RF component models in VHDL-AMS for time domain simulation. This library includes mainly the transmission line (TL) and the RF transceiver components such as the low noise amplifier (LNA), the mixer and the local oscillator (LO). The models consider the conventional parameters describing their performances including the non-linearities, the noise and the bandwidth of the LNA and the mixer. Leakages between ports are also considered for the mixer. The LO model considers the traditional parameters, more importantly its phase noise. The originality of the TL model is the modeling of the skin effect on a wide frequency range for time domain simulations. All the models are validated. Global simulations are performed to demonstrate the interest to accurately model the components of the RFNoC. The developed library is used here for wired RFNoC, however it can be used for all other wired and wireless RF communication system.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0975-6
Issue No: Vol. 92, No. 1 (2017)

• A programmable 40 Gb/s SST driver with high-frequency signal-boost
capability in 28 nm CMOS
• Authors: Khaldoon Abugharbieh; Karam Gharbieh
Pages: 115 - 129
Abstract: A programmable high-speed source-series-terminated driver with signal boost capability is presented. The driver uses only one main input data tap and is divided into main units and auxiliary units. A passive high pass filter is utilized to detect data transitions and control the inputs of the auxiliary units to enable a programmable amplitude boost for the output signal. The corner frequency of the high pass filter is adjusted depending on the data rate. Further, the amount of the high frequency signal boost can be adjusted depending on the loss of the channel. HSPICE simulations are used to demonstrate the performance of the driver at 10, 20 and 40 Gbps data rates. At 40 Gbps, the driver is capable of equalizing a PRBS9 data pattern signal through a channel that has a loss of 9 dB. At worst case conditions and 40 Gbps date rate, the driver achieves a differential eye-opening amplitude of 201 mVppd and an eye-opening of 0.952 UI. The driver is designed using 28 nm CMOS process and uses a nominal 1 V supply voltage. It consumes a maximum of 12 mW of at-speed power.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0967-6
Issue No: Vol. 92, No. 1 (2017)

• FVF LDO regulator with dual dynamic-load composite gain stage
• Authors: Chengpeng Li; Pak Kwong Chan
Pages: 131 - 140
Abstract: A low-voltage output-capacitorless low-dropout regulator using dual dynamic-load composite gain stage for flipped voltage follower topology is presented. It also incorporates a delay discharge circuit which aims to reduce the long discharge time arising from the large capacitive load, thus achieving the overshoot time reduction and sustaining fast transient characteristic when driving low-power digital system with internal heavy capacitive load requirement. The regulator can support a minimum of 0.75 V input voltage with 0.5 V output voltage. It consumes 49.4 µA whilst maintaining the stability for a capacitance load range from 470 pF to 10 nF. For a current load transient from 0 to 10 mA with 200 ps edge time, the settling time is 0.38 µs for the load capacitance of 3 nF. The obtained transient figure-of-merit is 0.42 mV. This transient metric outperforms the representative prior-art reported works.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0972-9
Issue No: Vol. 92, No. 1 (2017)

• An ultra-low power CMOS DC–DC buck converter with double-chain
digital PWM technique
• Authors: Sandeep Kumar; Jinwong Choi; Hanjung Song
Pages: 141 - 149
Abstract: In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0983-6
Issue No: Vol. 92, No. 1 (2017)

• A low power sub-BGR with multi-curvature self-compensation
• Authors: Junchao Mu; Lianxi Liu
Pages: 151 - 158
Abstract: This paper proposes a low power sub bandgap reference (sub-BGR) with a novel multi-curvature self-compensation. The proposed circuit generates a curvature-compensation-less reference voltage (VREF_NC), which is compared with the emitter–base voltage of a PNP transistor to generate a pair of complementary curvature currents. The curvature currents are used to compensate the temperature coefficient (TC) of the voltage VREF_NC itself, resulting in a low-power and low-TC sub-BGR. The proposed circuit is implemented in a standard 65 nm complementary metal oxide semiconductor process. Simulation and measured results show the total power consumption is about 230 nW at the minimum supply voltage of 1.0 V. The power supply rejection ratio at low frequency is less than −66 dB. After trimming, the average TC of 23 ppm/°C in the temperature range of −45 to 125 °C and the accuracy of ± 0.15% (σ/µ) can be achieved.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0963-x
Issue No: Vol. 92, No. 1 (2017)

• Design of 0.5 V voltage-combiner based OTA with 60 dB gain
250 kHz UGB in CMOS
• Authors: Antaryami Panigrahi; Abhipsa Parhi
Pages: 159 - 165
Abstract: A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of $$2\,\frac{{\text{V}}}{{\text{V}}}$$ , this voltage combiner can produce gain more than $$5\,\frac{{\text{V}}}{{\text{V}}}$$ . So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than $$55^{\circ }$$ for a typical load of 10 pF. The input referred noise is $$150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}$$ at 10 Hz and slew rate $$0.02\,{\text{V}}{/}\upmu{\text{s}}$$ for 10 pF load.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0965-8
Issue No: Vol. 92, No. 1 (2017)

• New CMOS realization of high performance Voltage Differencing Inverting
Buffered Amplifier and its filter application
• Authors: Shweta Kumari; Maneesha Gupta
Pages: 167 - 178
Abstract: This paper describes a high performance voltage differencing inverting buffered amplifier (VDIBA). The transconductance of the proposed circuit is enhanced by using positive feedback technique with only two extra transistors used in active load. Moreover, the bandwidth of proposed circuit is enhanced by using resistive compensation technique. The performance of proposed VDIBA is demonstrated by detailed frequency analysis. Furthermore, it is shown that the transconductance can be enhanced up to 4.61 mS at biasing current of 300 µA. In addition, a third order low pass filter is given as an application example to confirm the high performance of the proposed VDIBA. The proposed low pass filter operates at natural pole frequency of 15 MHz. The proposed VDIBA and its filter application are implemented using TSMC 90 nm CMOS technology in Cadence virtuoso schematic composer at ±0.6 V supply voltage.
PubDate: 2017-07-01
DOI: 10.1007/s10470-017-0968-5
Issue No: Vol. 92, No. 1 (2017)

• A highly linear wideband 0.3-to-2.7 GHz variable-gain amplifier
• Authors: Vahid Asgari; Leonid Belostotski
Pages: 473 - 478
Abstract: A design of a differential variable-gain amplifier (VGA) with high IP3 (third-order intercept point) is discussed. To improve IP3, the third-order intermodulation products, which are generated by both an intrinsic third-order nonlinearity and a second-order interaction of a transistor, are minimized by using a nonlinear conductance. Unlike prior methods, the proposed method enables the achievement of both constant and broadband IP3 for various VGA gain settings. A design example with virtual but realistic BSIM4 transistor models is discussed to verify the analysis. The resultant amplifier example was designed and simulated in a 28-nm FDSOI CMOS technology. The amplifier achieved more than 15 dBm input-referred IP3 across a 2.4-GHz bandwidth from 0.3-to-2.7 GHz with a variable gain of 0-to-8.5 dB while consuming 3.3 mA from a 1.5-V supply.
PubDate: 2017-06-01
DOI: 10.1007/s10470-017-0948-9
Issue No: Vol. 91, No. 3 (2017)

• Design and analysis of low-power and area efficient N-bit parallel binary
comparator
• Authors: Chang Chua; R. B. N. Kumar; B. Sireesha
Abstract: This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR–NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180nm—technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto $$25\%$$ , area (number of transistors) reduces upto $$36\%$$ and improves the delay performance $$27\%$$ compared to existing technique.
PubDate: 2017-06-09
DOI: 10.1007/s10470-017-0996-1

• A 500 MHz low offset fully differential latched comparator
• Authors: Saeed Naghavi; Niloofar Sharifi; Mozhdeh Nematzadeh; Tohid Moradi Khanshan; Adib Abrishamifar; Zia Daei Kuzekanani; Jafar Sobhi
Abstract: A fully differential latched comparator using a new offset cancellation technique is presented. The comparator consists of three stages: the input pre-amplifier, a positive feedback or latch stage and the offset cancellation circuitry. The effect of kick-back noise can be significantly reduced by using a pre-amplifier stage. Also, the offset and noise of the latch and offset cancellation stages are attenuated by the gain of the pre-amplifier when referred to the input. Latches regenerate faster than pre-amplifiers and provide a full swing digital output for the comparator. The last stage is the offset cancellation circuitry. The main advantage of the proposed offset cancellation technique is that it does not need to make any interrupt in normal operation of comparator to eliminate offset error. As a result, higher speeds for the comparator can be achieved. Moreover, the power consumption of the proposed offset cancellation circuitry is negligible compared to the overall power consumption. In order to evaluate the performance of the comparator, simulations are performed in a 0.18 μm standard CMOS technology. Simulation results show that the offset values of the pre-amplifier and latch stages are significantly eliminated by this cancellation technique and only about 450 μV offset voltage will be referred to the input due to offset error of the offset cancellation circuitry. The proposed comparator operates at 500 MHz clock frequency and dissipates 373 μW from a 1.8 supply. Also, it has a propagation delay of 138 ps and kick-back noise of 0.54 mV.
PubDate: 2017-06-08
DOI: 10.1007/s10470-017-0998-z

• Sorting-free digital median filter for SOCs
• Authors: Saleh Abdel-hafeez; Behrooz Parhami; Arwa Damir
Abstract: In this work, we propose a new median-finding algorithm which computes the median value in an input list of integers on-the-fly, without any data-sorting operations. We present a complete digital CMOS implementation, associated timing diagrams, and a formal mathematical proof, which show the overall average number of clock cycles for median-finding to be linearly proportional to the input length, that is, O(N) average-time complexity, when N is less than about 100. Hence, our proposed sorting-free median algorithm is suitable for practical applications on 3 × 3 and 5 × 5 image scan matrices, which are in common use for hand-held devices and entertainment graphics applications. Our proposed hardware precludes the need for SRAM memory or complex circuitry, such as pipelining structures, but rather uses simple registers to hold the input values, performing comparison-swapping on 3 values, along with counting, to derive the median value. There is no restriction on the input sequence with regard to having repeated elements. We evaluate an ASIC design of our sorting-free median algorithm using 90 nm TSMC technology, with 1 V supply voltage and a clock frequency of 2 GHz, on example cases of 3 × 3 (9 values) and 5 × 5 (25 values) image-scan matrices. The resulting designs have a minimum transistor-count ranging from 3202 to 5203. Results show that our sorting-free median algorithm, when used on 512 × 512 images with 8-bit pixels, takes 0.364 and 1.394 ms to scan the complete image using 3 × 3 and 5 × 5 scan matrices, respectively, with the associated power consumption ranging from 3.24 to 1.66 mW.
PubDate: 2017-06-08
DOI: 10.1007/s10470-017-0991-6

• SDTSPC-technique for low power noise aware 1-bit full adder
• Authors: Preeti Verma; Ajay K. Sharma; Arti Noor; Vinay S. Pandey
Abstract: This paper presents a new design named as SDTSPC (Stacked and diode transistor based TSPC) logic for 1-bit full adder to achieve low power noise aware design. Gated transistors are used as stacked transistors from supply to ground path in both sum and carry circuits. One diode connected transistor is placed in series with evaluation transistor to achieve further improved performance in terms of reduced bouncing noise. Analysis is done for power consumption and propagation delay during active and idle mode of operation for both low (25 °C) and high (110 °C) die temperature. Comparing SDTSPC with recently proposed static 1-bit hybrid full adder we get more than 90% improvement in PDP while 30.7% improvement when compared to dynamic TSPC based 1-bit full adder. Corner analysis verifies that our design has the least effect of process exaggeration on PDP and with varying temperature and supply voltage this design keeps lowest value of current among other techniques. SDTSPC design has reduced ground and supply bounce noise. The proposed design is also compared with several previously proposed designs and it is found to have best power delay product (PDP). Further, SDTSPC technique is implemented on 32-bit ripple carry adder as an prolongation of technique.
PubDate: 2017-06-05
DOI: 10.1007/s10470-017-0994-3

• A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low
data rate applications
• Authors: Nicolas Dehaese; Inès Ben Amor; Ndiogou Tall; Jean Gaubert; Rémy Vauché; Sylvain Bourdel
Abstract: A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of −92 dBm for a 10−3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).
PubDate: 2017-05-05
DOI: 10.1007/s10470-017-0985-4

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