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 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [7 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2350 journals]
• Active inductor based tunable multiband RF front end design for UWB
applications
• Authors: J. Manjula; S. Malarvizhi
Pages: 195 - 207
Abstract: This paper presents a multiband RF front end, designed with cascading a ultra wide band (UWB) low noise amplifier and a tunable band pass filter (BPF). The tunable BPF is designed using active inductors. A controllable current source is used to tune the BPF to select the bands of UWB range. The proposed RF front end is tuned to select the center frequencies 4, 5, 6.6, 7.96 and 10 GHz of UWB range. The obtained UWB bands are able to achieve a gain greater than 20 dB and a noise figure less than 5 dB. The designed RF front end consumed an average power of 23 mW.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1168-7
Issue No: Vol. 95, No. 2 (2018)

• Charge pump with reduced current mismatch for reference spur minimization
in PLLs
• Authors: Debdut Biswas; Tarun Kanti Bhattacharyya
Pages: 209 - 221
Abstract: In this article, a charge pump circuit featuring minimal mismatch between its up and down currents is proposed. In conventional charge pumps, where error amplifiers are used in feedback, the factor that hinders exact current matching is the offset voltage of the error amplifier. In the proposed design, the input offset voltage is computed and additional current delivering/comsuming branch is implemented to supplement for the error current. The new charge pump requires a few error amplifiers and a dynamic comparator for its operation. Simulations considering process variations show current mismatch of less than 20 nA even at the worst case event. The proposed charge pump has been utilized in PLL circuits to reduce reference spurs and simulations of these PLLs show remarkable spur reduction.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1163-z
Issue No: Vol. 95, No. 2 (2018)

• Miniaturized microstrip lowpass filter using cylindrical-shaped resonators
for integrated applications
Pages: 223 - 229
Abstract: A novel compact microstrip lowpass filter is presented in this paper. The structure uses stepped impedance and radial patches and it has the − 3 dB cut-off frequency at 4.39 GHz. The proposed lowpass filter has a wide rejection band from 6 to 30 GHz with rejection level more than − 20 dB. It has also other advantages such as: low insertion-loss < 0.1 dB and high return-loss more than 22 dB in 80% of the passband. The circuit size of the presented filter is about 90 mm2. Such important advantages make the proposed lowpass filter applicable to be integrated in many high frequency circuits such as power amplifiers, oscillators, couplers and power dividers. It also can block the unwanted video transmitter interference nearby 4 GHz such as implementing between transmitter and antenna. The lowpass filter has simulated and fabricated and a good agreement was seen between the simulation and fabrication results.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1176-7
Issue No: Vol. 95, No. 2 (2018)

• An accurate digital baseband predistorter design for linearization of RF
power amplifiers by a genetic algorithm based Hammerstein structure
Pages: 231 - 247
Abstract: In this paper, a novel digital predistorter design based on the Hammerstein structure is proposed in order to linearize radio frequency power amplifiers. A genetic algorithm optimization method has been proposed to accurately identify the coefficients of a Wiener model for the power amplifier. Digital predistorter design based on the proposed Hammerstein model has been carried out according to the accurate Wiener model. The validation of the suggested model is carried out using the simulation of the power amplifier and the digital predistortion excited by 64QAM signals in the advanced design system software. According to the simulation results, the criterion of an adjacent channel power ratio decreased by about 16 dB. The simulation results show the adjacent channel power ratio of almost − 46 dBc. In order to assess the feasibility of the proposed predistorter, it is completely implemented in the Kintex FPGA using Vivado HLS. This proposed model enables a more accurate modeling of nonlinear distortion and memory effects compared to the previous linearization methods. This paper presents the new linearization method using the genetic algorithm based Hammerstein structure.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1173-x
Issue No: Vol. 95, No. 2 (2018)

• Performance study of a fractal UWB MIMO antenna for on-body WBAN
applications
• Authors: Shrivishal Tripathi; Akhilesh Mohan; Sandeep Yadav
Pages: 249 - 258
Abstract: In this paper, a fractal ultrawideband multiple-input–multiple-output antenna is proposed and its characteristics are studied in free space as well as in the proximity of on-body wireless body area network scenario. The performance of the wideband antennas are affected strongly in the proximity of the human body. Koch fractal geometry is used at the outer edges of basic octagonal geometry in the design, which helps to achieve desired miniaturization, wideband and stable radiation pattern. The presented antenna has a compact size of 25 mm × 40 mm. In addition, the effect of body tissues on antenna characteristics is analyzed by a four layered (skin, fat, muscle and bone) human tissue model. The comparative analysis of S21 is performed at a various body parts position such as abdomen, near forehead and chest with different antenna orientations.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1138-0
Issue No: Vol. 95, No. 2 (2018)

• A 2.4 GHz ISM-band highly digitized receiver based on a variable gain LNA
and a subsampled $$\varSigma \varDelta$$ Σ Δ ADC
• Authors: Delaram Haghighitalab; Diomadson Belfort; Alp Kiliç; Aziz Benlarbi-Delaï; Hassan Aboushady
Pages: 259 - 270
Abstract: In this paper, we present a complete multi-standard receiver based on a variable-gain LNA and an RF subsampled Sigma-Delta ADC. The receiver includes an RF digital down-conversion mixer and a polyphase multistage multi-rate decimation filter. The receiver is measured for 3 different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79, 73 and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1136-2
Issue No: Vol. 95, No. 2 (2018)

• Analysis of multistage amplifiers with hybrid cascode feedforward
compensation using a modified model for load impedance
Pages: 271 - 282
Abstract: Hybrid cascode feedforward compensation (HCFC) is an effective technique to stabilize nano-scale three-stage amplifiers driving ultra-large load capacitors. It divides the compensation capacitance and shares it between two high-speed local feedback loops embedded within the amplifier core. In this article, a systematic approach to analyze the transfer function and to evaluate the pole expressions of nano-scale HCFC amplifiers is presented. For the first time, the equivalent output impedance is successfully modeled to approximate the complicated transfer function of the HCFC amplifier without the need for lengthy pencil-and-paper calculations. An HCFC amplifier is designed and simulated in 90-nm CMOS technology, to verify the effectiveness of the new analytic approach. The simulated transfer function of the amplifier is almost identical to a calculated transfer function derived based on the new model.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1179-4
Issue No: Vol. 95, No. 2 (2018)

• A current-reuse biomedical amplifier with a NEF &lt; 1
• Authors: Matías R. Miguez; Joel Gak; Alfredo Arnaud; Alejandro Raúl Oliva; Pedro Julián
Pages: 283 - 294
Abstract: Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-reuse technique will be utilized to exceed this limit in a very efficient CMOS amplifier. A micro-power, ultra-low-noise amplifier, aimed at electro-neuro-graph signal recording in a specific single-channel implantable medical device, is presented. The circuit is powered with a standard medical grade 3.6 V(nom) secondary battery. The amplifier input stage stacks twelve differential pairs to maximize current-reuse. The differential pair stacking technique is very efficient: allows most of the energy to be dissipated in the input transistors that amplify and not in mirror or bias transistors, and allows also the input transistors to operate with a reduced VDS just above saturation. The amplifier was implemented in a 0.6 μm technology, it has a total gain of almost 80 dB, with a 4 kHz bandwidth. The measured input referred noise is 4.5 nV/Hz1/2@1 kHz, and 330 nVrms in the band of interest, with a total current consumption of only 16.5 μA from the battery (including all the 4 stages and the auxiliary circuits). The measured NEF is only 0.84, below the classic NEF = 1 limit.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1175-8
Issue No: Vol. 95, No. 2 (2018)

• A novel algorithm to study the impact of the mismatch on analog building
blocks: a case study in basic 35 nm CMOS amplifiers
• Authors: Hamid Reza Shokouhfar; Hamed Jooypa; Daryoosh Dideban
Pages: 295 - 306
Abstract: In this paper, the context of modeling of the impact of mismatch and statistical variations on analogue circuit building blocks is emphasized. The aim is to develop a new algorithm which predicts the statistical behavior of important parameters of an amplifier including output resistance, voltage gain and trans-conductance. The relative error of standard deviation of statistical parameters will remain less than 5% compared with the most accurate Monte-Carlo (MC) simulations using atomistic library model-cards. In comparison with other models which are based on the normal distribution of parameters, the proposed model does not need this limiting presumption. On the other hand, the proposed algorithm is more efficient compared with time consuming MC atomistic simulations.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1133-5
Issue No: Vol. 95, No. 2 (2018)

• A SiGe:C BiCMOS dual down converter for MIMO wireless infrastructure with
configurable current consumption and linearity
• Authors: Gesualdo Alessi; Francesco Clerici
Pages: 307 - 313
Abstract: This paper presents a dual RF down converter suitable for Multiple-Input and Multiple-Output infrastructure applications. The proposed architecture features a CMOS tapered buffer as local oscillator driver with a programmable supply voltage, provided by an embedded low dropout regulator. This approach allows scaling current consumption depending on linearity requirements. The RF path uses a balun with programmable tuning capacitors for single-to-differential signal conversion and $$50\text{-}\Omega$$ input matching. A MOSFET passive mixer and a high-voltage (5 V) bipolar intermediate frequency amplifier complete the signal path. The circuit is fabricated in a SiGe:C BiCMOS process, occupies an area of $$2.8\, \text{mm} \, \times \, 2.5\, \text{mm}$$ , and has been assembled in a $$6\, \text{mm} \, \times \,6\, \text{mm}$$ , 40-pin, quad flat no-lead (QFN) package.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1132-6
Issue No: Vol. 95, No. 2 (2018)

• An integrated charge-transfer relaxation oscillator without comparator
• Authors: Yanzhao Ma; Song Fang; Kai Cui; Danghui Wang; Xiaoya Fan
Pages: 315 - 323
Abstract: This letter presents a charge-transfer relaxation oscillator that achieves ultra-low power operation without comparator. The oscillator is implemented by charging or discharging the negative plate of the capacitor to a reference voltage through charge-transfer technique and the positive plate of the capacitor by a constant reference current, respectively. A special sawtooth waveform is generated, and a pseudo-inverter chain with delay compensation is adopted to determine the oscillation state. In the proposed structure, a conventional comparator has been eliminated to avoid comparator offset effect. The oscillator has been implemented with TSMC 0.18  $$\upmu$$ m CMOS process. The circuit operates in subthreshold region and consumes a total power of 85 nW. The circuit demonstrates a frequency variation less than 0.8%/V over 1.2–1.8 V, leading to a temperature coefficient of 33 ppm/ $$^{\circ }$$ C over − 40 to 80  $$^{\circ }$$ C.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1144-2
Issue No: Vol. 95, No. 2 (2018)

• A new CMOS design of high transconductance current follower
transconductance amplifier and its applications
• Authors: Shweta Kumari; Maneesha Gupta
Pages: 325 - 349
Abstract: In this work, a new CMOS implementation of high transconductance current follower transconductance amplifier (CFTA) is proposed. The proposed CFTA uses current starving technique along with an auxiliary unit (AU) to enhance transconductance performance. The cross-drain-coupled MOSFETs are also used in AU which further enhances transconductance of proposed circuit. The proposed CFTA provides higher transconductance and wider tuning range without affecting its output swing and bandwidth performance. The proposed CFTA provides transconductance of 11.3 mS, dissipates 1.8 mW power and operates at ± 0.6 V supply voltage. A current mode third order quadrature oscillator and biquad filter have been designed and simulated, to validate the performance of proposed circuit. The workability of proposed CFTA and its applications have been verified by using Cadence virtuoso schematic composer with TSMC 0.18 µm process parameters.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1162-0
Issue No: Vol. 95, No. 2 (2018)

• A new CFOA-based negative group delay cascadable circuit
• Authors: Muhammad Taher Abuelma’atti; Zainulabideen Jamal Khalifa
Pages: 351 - 355
Abstract: This paper presents a simple electronic circuit which provides negative group delay (NGD). The proposed circuit is built around the current-feedback operational-amplifier and uses grounded resistors and capacitors. The proposed circuit has a high input impedance and a low output impedance. Thus, obtaining relatively long NGDs is feasible by cascading several circuits. Experimental and simulation results that confirm the functionality of the proposed circuit are included.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1172-y
Issue No: Vol. 95, No. 2 (2018)

• A CMOS multi-gain transconductance amplifier and its applications
• Authors: Hussain Alzaher
Pages: 357 - 364
Abstract: Transconductance amplifier (gm) based circuits are attractive due to their inherent programmability features. Single output gm’s are often replaced by multi-output gm’s to reduce the number of active devices for a given application. However, this usually results in losing the circuit programmability features. This work shows that this problem can be circumvented through adopting a new programmable multi-gain gm. The advantages of the proposed multi-gain gm are demonstrated using two filter design examples. They show that the proposed multi-gain gm reduces the number of active devices by two-third compared with their single output gm based counterparts while maintaining their versatile programmability characteristics. Experimental results obtained from a 0.18 μm CMOS process for one of the applications are provided.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1178-5
Issue No: Vol. 95, No. 2 (2018)

• A chopper-stabilized source follower coupling based low-pass filter with
noise reduction
• Authors: Yang Xu; Un-Ku Moon
Pages: 365 - 369
Abstract: A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single stage with no use of operational amplifiers. Chopper stabilization technique is utilized to reduce 1/f noise for minimizing the in-band integrated noise. Implemented and simulated in a 0.18 μm CMOS process, the 3rd-order LPF achieves a − 3 dB bandwidth of 20 MHz with a 280 μA total current from a 1.4 V supply voltage, defining a power-per-pole/bandwidth efficiency of 6.5 μW/MHz. The output noise density at low frequencies is largely reduced with chopper stabilization technique. The integrated output noise from 10 kHz to 2 MHz is minimized from 22.47 to 7.04 μVrms, with a 10.1 dB improvement. The averaged output noise density over the filter bandwidth is 9.4 nV/√Hz, which is mostly contributed by thermal noise of transistors.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1185-6
Issue No: Vol. 95, No. 2 (2018)

• Correction to: A four-quadrant current multiplier/divider cell with four
transistors
• Authors: Ahmed Elwakil; Brent Maundy; Mohammed Balla Elamien; Leonid Belostotski
Pages: 371 - 371
Abstract: The original version of this article unfortunately contained a mistake. The co-authors’ affiliation details were incorrect in the original publication of this article.
PubDate: 2018-05-01
DOI: 10.1007/s10470-018-1157-x
Issue No: Vol. 95, No. 2 (2018)

• On-chip active filter in GaAs technology for wireless communication
systems
• Authors: L. Pantoli; V. Stornelli; G. Leuzzi; Hongjun Li; Zhifu Hu
Abstract: In this work we present the design of a GaAs monolithic active filter. It is based on a 0.13 μm pHMET technology process provided by HSRI and it has been conceived for RF practical applications, being defined by typical specifications of modern wireless communication systems. The design is based on the use of active inductors in place of spiral inductors, significantly improving the overall performance of the filter. Each active inductor makes use of only one active device slightly affecting the overall power consumption. The filter has been optimised for operating in the bandwidth (1800–2100 MHz) with a 3 dB bandwidth of 30 MHz and a very high slope factor. The 1 dB compression point is − 8 dBm and it is obtained with a DC power consumption of 120 mW.
PubDate: 2018-04-27
DOI: 10.1007/s10470-018-1198-1

• Oxford circuits and systems conference
• Authors: Bhaskar Choubey; Khaled Hayatleh; Alex Pappachen James
PubDate: 2018-04-25
DOI: 10.1007/s10470-018-1193-6

• A compensation scheme for non-ideal circuit effects in biomedical
impedance sensor
• Authors: Yan Hong; Wang Ling Goh; Yong Wang
Abstract: The accuracy of an I/Q based biomedical impedance sensing sensor (IQBIS) suffers significantly from the PVT effects of the analog front-end, such as the amplitude errors of the stimulation signals, gain mismatches, amplitude and phase imbalances of in-phase (I) and quadrature (Q) signals, etc. These practical effects will severely impede the system performance if handled improperly. In this paper, the degradations of sensing performance by such imperfections are mathematically analyzed and quantified. Following theoretical studies, a digitally controlled correction approach is proposed to finely alleviate these impairments. The performance of the proposed scheme had been verified using Simulink and MATLAB. With the proposed error correction scheme, the accuracy is improved by at least 17 times compared to that of the typical IQBIS, for both real and imaginary values of impedance. Thus, the proposed method is very useful for IQBIS, in resisting degradation in sensing accuracies due to the process-voltage-temperature (PVT) effects.
PubDate: 2018-04-25
DOI: 10.1007/s10470-018-1182-9

• Compact substrate integrated waveguide sensor for liquids permittivity
measurement
Abstract: A compact substrate integrated waveguide (SIW) liquids permittivity sensor structure that utilizes half-mode (HM) and slow-wave (SW) techniques for the miniaturization of SIW sensor is presented in this paper. First, HM miniaturization technique is applied to SIW resonator cavity. Sensor width is reduced by 50% in comparison to the conventional resonator. Due to the complexity of the relationship between the complex permittivity of the substrate and liquids under test, artificial neural network tool is used as a simple and fast method to determine liquids’ complex permittivity through the measured resonant frequency and unloaded quality factor. The sensor is fabricated, and good agreement with simulations is observed according to the obtained experimental results. In the second step, SW and HM techniques are applied to the SIW sensor. The application of the HM and SW techniques indicate that an increase in sensor miniaturization while obtaining a better quality factor could be achieved. Furthermore, HM-SW-SIW is not fabricated, and we are satisfied with simulation results since we have fabricated other components. Moreover, good correspondence between the measurement and simulation results is obtained. Finally, a comparison between the structures presented in this paper and those published previously is made, demonstrating that a minimum of 25% miniaturization is achieved while maintaining acceptable characteristics.
PubDate: 2018-04-24
DOI: 10.1007/s10470-018-1192-7

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