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 Analog Integrated Circuits and Signal ProcessingJournal Prestige (SJR): 0.211 Citation Impact (citeScore): 1Number of Followers: 7      Hybrid journal (It can contain Open Access articles) ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030 Published by Springer-Verlag  [2349 journals]
• A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS
• Authors: Mustafa Kilic; Themistoklis G. Mavrogordatos; Yusuf Leblebici
Pages: 397 - 404
Abstract: In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds for the remaining 4 LSBs. The DAC capacitance at the front-end remains small enough to achieve high sampling rate with increased input bandwidth. Two asynchronously clocked alternate comparators are used additionally to improve conversion speed. The ADC is designed and simulated in 28 nm FD-SOI CMOS. It consumes 4.1 mW from a 1 V supply, while achieving a SNDR of 52.1 dB and a Figure-of-Merit of 11.4 fJ/conversion-step.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1222-5
Issue No: Vol. 97, No. 3 (2018)

• Design of a fA wide dynamic range ADC for current sensing
• Authors: Evgenia Voulgari; Matthew Noy; Francis Anghinolfi; François Krummenacher; Maher Kayal
Pages: 405 - 415
Abstract: Current sensing is important in various applications. The Utopia 2 Application Specific Integrated Circuit (ASIC) was developed in AMS 0.35 $$\upmu \hbox {m}$$ technology for radiation monitoring based on ionization chambers. The ASIC is able to measure current equal to 1 femtoampere (fA) after active leakage current compensation. The compensation is achieved with a second dummy compensating channel that is matched to the measuring channel. The ASIC was also designed to cope with input currents that span over nine decades of dynamic range. The analog to digital conversion is performed with charge balancing and counting. The maximum current that is equal to 5 $$\upmu \hbox {A}$$ can be measured after the introduction of a second range. The system has been characterized at a certified laboratory and is able to sense currents from 1 fA up to 5 $$\upmu \hbox {A}$$ .
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1224-3
Issue No: Vol. 97, No. 3 (2018)

• Low power SAR ADC switching without the need of precise second reference
• Authors: Dmitry Osipov; Steffen Paul
Pages: 417 - 425
Abstract: In this paper a simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the proposed method does not require the intermediate voltage to be accurate. The implementation of digital control and an intermediate voltage-level generator is considered. To evaluate the reduction in switching energy compared to the conventional monotonic switching procedure, the behavioral model of a 10-bit ADC was examined. The additional digital logic, voltage generator, and capacitive DAC were modeled at a transistor level using a 65 nm STM design kit. Simulation results and the subsequent power efficiency gains are presented.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1225-2
Issue No: Vol. 97, No. 3 (2018)

• A 14-bit 250 kS/s two-step inverter-based incremental $$\varSigma \varDelta$$ Σ Δ ADC for CMOS image sensor in $$0.18\,\upmu \hbox {m}$$
0.18 μ m technology
• Authors: Pierre Bisiaux; Caroline Lelandais-Perrault; Anthony Kolar; Filipe Vinci dos Santos; Philippe Benabes
Pages: 427 - 435
Abstract: This paper presents a 14-bit Incremental Sigma-Delta $$(\varSigma \varDelta)$$ analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same $$\varSigma \varDelta$$ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in $$0.18\,\upmu \hbox {m}$$ CMOS technology. The simulation is performed with a 1.8 V voltage supply, a 20 MHz system clock frequency and an oversampling ratio (OSR) of 70, and achieves a power consumption is $$460 \, \upmu \hbox {W}$$ , a SNDR of 85.4 dB at a sampling rate of 250 kS/s.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1238-x
Issue No: Vol. 97, No. 3 (2018)

• Architecture optimization for energy-efficient resolution-scalable
• Authors: Thomas Bos; Komail Badami; Wim Dehaene; Marian Verhelst
Pages: 437 - 448
Abstract: Low power analog-to-digital converters (ADCs) in energy constrained devices, such as wireless sensor readout modules, often target dynamic resolution scalability with application context to reduce the average power consumption. This work implements such an 8–12-bit resolution scalable ADC, using an oversampling and noise-shaping successive approximating register (SAR) architecture. This architecture is selected for its high power efficiency after a detailed comparison of various resolution enhancing techniques within the SAR framework. Specifically, in this paper, three resolution enhancing techniques are reviewed and compared on their energy usage namely: the majority voting, the oversampling, and the oversampling with noise shaping SAR ADC. Furthermore, the proposed resolution scalable ADC simplifies the design of the noise shaping filter by enabling the use of a first order switched-capacitor low-pass filter for shaping the comparator noise and the in-band quantization noise. The ADC design also alleviates the matching concerns by using only an 8-bit capacitive digital-to-analog converter (DAC) for a maximum 12-bit resolution, or 11-bit effective number of bits (ENOB). The architecture can be configured to allow an operation from 8-bit traditional SAR ADC up to an 11-bit ADC by enabling the oversampling and noise shaping loops within the SAR architecture. This ADC is designed to operate with up to 320 kS/s and achieves a power scaling from 80 nW to 1.5  $$\upmu$$ W, resulting in an steeper energy-ENOB scaling trend compared to state-of-the art resolution scalable ADCs.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1235-0
Issue No: Vol. 97, No. 3 (2018)

• Switched-capacitor high-speed emulator for real-time fault location in
electrical power systems
• Authors: François Gaugaz; François Krummenacher; Maher Kayal
Pages: 449 - 456
Abstract: This research presents a discrete-time transmission line model based on the propagation of travelling waves. In this approach, the transmission line is emulated by means of many interconnected unit delay cells implemented with switched-capacitor (SC) circuits. The accuracy and limitations of this method is compared to existing transconductance–capacitor solutions and is evaluated in the frame of a novel power network fault location method based on the electromagnetic time-reversal principle. The impact of the non-ideal effects associated to analog CMOS SC circuits, such as amplifier finite gain, offset and switch charge injection is evaluated in the same context. A possible application of the model for the simulation of interconnected or multi-conductor lines is also discussed. After an AMS 0.35 µm process implementation, it is shown that the present method allows a fault location within 1% resolution and is a hundred times faster than nowadays digital solutions. This speed improvement allows a fault location within 160 ms, making thus real-time applications realistic.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1226-1
Issue No: Vol. 97, No. 3 (2018)

• Analysis and design of impulse signal generator based on current-mode
excitation and transmission line resonator
• Authors: Parit Kanjanavirojkul; Nguyen Ngoc Mai-Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada
Pages: 457 - 470
Abstract: A novel pulse generation method based on current-mode excitation circuit and transmission line resonator is proposed. The technique aims at an efficient pulse generation with high center frequency for applications with low duty cycle. It features quick starting time and zero stand-by power. As opposed to conventional voltage-mode pulse generation, the proposed current-mode technique reduces loss from parasitic capacitance of the excitation circuit, so that the energy conversion efficiency is increased. In addition, the excitation circuit size is smaller compared to the voltage-mode. The analyses of Q factor, oscillation frequency and energy conversion efficiency are discussed. The design methodology for the pulse generator is explained, followed by the demonstration of three pulse generator prototypes at 12 GHz oscillation frequency. The pulse generator is implemented by 0.18  $$\upmu \hbox {m}$$ CMOS flipped on quartz substrate. The measurement results show the energy conversion efficiency of 3.13 %, with the energy consumption of 1.06 pJ/pulse.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1236-z
Issue No: Vol. 97, No. 3 (2018)

• An accurate time-to-digital converter based on a self-timed ring
oscillator for on-the-fly time measurement
• Authors: Assia El-Hadbi; Abdelkarim Cherkaoui; Oussama Elissati; Jean Simatic; Laurent Fesquet
Pages: 471 - 481
Abstract: This paper proposes a new architecture of a time-to-digital converter (TDC) based on a self-timed ring (STR) oscillator with sub-gate delay resolution. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Exploiting the phase difference between events propagating in the same STR without collision, this TDC benefit from a uniform phase distribution. Thus, under certain conditions, a regular time base can be generated and a compact readout algorithm can be applied. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. As a proof-of-concept, an STR-based TDC with only 9-stages has been simulated using 28 nm FDSOI technology. A time resolution of 8.9 ps has been achieved. Without using calibration, the measured DNL and INL are 0.44 and 0.40 LSB, respectively. Simulation results point out the advantage of this TDC in terms of measurement accuracy and state the limit of the on-the-fly measurement according to the dependency between the jitter and the time resolution.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1223-4
Issue No: Vol. 97, No. 3 (2018)

• A low-power high-performance digital predistorter for wideband power
amplifiers
• Authors: Venkata Narasimha Manyam; Dang-Kièn Germain Pham; Chadi Jabbour; Patricia Desgreys
Pages: 483 - 492
Abstract: In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2  and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1263-9
Issue No: Vol. 97, No. 3 (2018)

• Distributed mixed-signal architecture for programmable smart image sensors
• Authors: Juliette Le Hir; Anthony Kolar; Filipe Vinci Dos Santos
Pages: 493 - 501
Abstract: Smart vision systems on a chip are promising for embedded applications. Currently, flexibility in the choice of integrated pre-processing tools is obtained at the expense of total silicon area and fill factor, which are otherwise optimized provided that the sensor performs a specific task. We propose a new architecture based on macropixel-level processing to improve the trade-off by using the same processing elements (PEs) for a whole group of pixels. In this paper, we show through transistor-level simulations the feasibility of using macropixel PEs. Their operative part is analog to avoid the bottleneck of analog to digital converters and has digital control which is distributed in and out of the matrix of pixels. PEs are designed to be suitable for coefficient-reconfigurable spatial and temporal filtering. Sharing electronics among several pixels and matching existing algorithms to the target architecture allow for such programmability without degrading too much pixel area nor fill factor.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1342-y
Issue No: Vol. 97, No. 3 (2018)

• Exploring approximations in 4- and 8- point DTT hardware architectures for
low-power image compression
• Authors: Guilherme Paim; Gustavo Madeira Santana; Leandro Mateus Giacomini Rocha; Leonardo Bandeira Soares; Eduardo Antônio César da Costa; Sergio Bampi
Pages: 503 - 514
Abstract: Due to the intensive use of discrete transforms in picture coding, the search for fast and power-efficient approaches for their hardware implementation gains importance. The Discrete Tchebichef Transform (DTT) represents a discrete class of the Chebyshev orthogonal polynomials, and it is an alternative for the Discrete Cosine Transform, commonly used in picture coding. High energy compaction and decorrelation are the main properties of the DTT. The state-of-the-art approximate DTT matrix is composed of 0, 1, − 1, 2, and − 2 coefficient values. In this work, we propose a new approximation for both the 4-point and 8-point integer DTT with better quality and power-efficiency. We explore the effects of coefficient truncation, whose values are 1/16, − 1/16, 1/8, − 1/8, 1/4, and − 1/4. Considering operations with integers, the smaller values of coefficients causes truncation in the internal transform calculations and leads to smaller values for the non-diagonal residues, which reduces the non-orthogonality. We have also selectively pruned the rows of the state-of-the-art approximate DTT matrix. The results show that the proposed pruned approximate DTT hardwired solutions increases the maximum frequency up to 5%, minimizes circuit area by over 30%, with savings of up to 32.4% in power dissipation with a higher compression ratio and fewer quality losses in the compressed image, when compared with state-of-the-art approximate DTT hardware designs.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1343-x
Issue No: Vol. 97, No. 3 (2018)

• Ambient RF energy harvesting system: a review on integrated circuit design
• Authors: Gabriel Chong; Harikrishnan Ramiah; Jun Yin; Jagadheswaran Rajendran; Wei Ru Wong; Pui-In Mak; Rui P. Martins
Pages: 515 - 531
Abstract: This paper presents a comprehensive review of ambient RF energy harvester circuitry working on integrated circuits. The review covers 3 main blocks in an RF energy harvesting system implemented on chip. The blocks are the rectifier, impedance matching circuit and power management unit. The review of each block includes its operational principle, reported state-of-the-art circuit enhancement techniques, and design trade-offs. We compare the circuits in each block with respect to the techniques adopted to improve the performances for RF energy harvesting. To identify the benefits and limitations associated with the architecture we discuss the advantages and disadvantages of the circuit topologies in each block of an ambient RF energy harvester.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1320-4
Issue No: Vol. 97, No. 3 (2018)

• Energy harvesting with pairs of variable capacitors without control
circuits
• Authors: Antonio Carlos M. de Queiroz; Nicolas A. Telles de Menezes
Pages: 533 - 544
Abstract: This work describes several electronic electrostatic generators that can be built using two pairs of complementary variable capacitors, in a way that dispenses control circuits for their operation. In all cases, a basic unstable generator based on an electrostatic charge multiplier is used to bias variable capacitors, and the current generated by these capacitors is then rectified and sent to the load. Experimental versions of the proposed generators were built using variable capacitors made with 3D-printing techniques, moved in a back-and-forth way by a small motor. As these generators operate at high impedance level, always with small currents, they are insensitive to the resistivity of the conductive plastic used to make the variable capacitors. Several new structures are presented, and their properties are evaluated theoretically and experimentally.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1253-y
Issue No: Vol. 97, No. 3 (2018)

• Efficient SSHI circuit for piezoelectric energy harvester uses one shot
pulse boost converter
• Authors: Sweta Kumari; Sitanshu Sekhar Sahu; Bharat Gupta
Pages: 545 - 555
Abstract: In this paper, a one shot pulse inductor boost converter is presented which provides 4 V output at 60 ms of delay using 0.15 V vibration source. Energy harvesting plays an important role in biomedical implants sensors where the extended life time is the most prominent factor. Synchronized switch harvesters on inductor (SSHI) comes into existence due to its highly efficient interface with energy harvesters. The main aim of this paper is to obtain high efficiency and maximum power extraction from piezoelectric energy harvester using SSHI and one shot pulse boost converter. This circuit does not require any external voltage and provides the controlled output with reduced power dissipation of approximately 10 nW and power consumption achieves between 1 and 10 mW. The start-up problem due to variable vibrational energy source is avoided by using one shot pulse inductor boost converter. This converter uses only one shot period for maximum charge transfer during first switching cycle. In 180 nm CMOS process, result shows that pulse boost converter can be directly powered from low voltage of 0.15 V with efficiency of ≈ 90% across the load of 6 µA current having switching frequency of 206 kHz. It also eliminates the problem of switching losses and reduces leakage current by saving board space and external components cost.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1218-1
Issue No: Vol. 97, No. 3 (2018)

• A 60 GHz phased array with measurement and de-embedding techniques
• Authors: Brock J. DeLong; Sandhiya Reddy Govindarajulu; Markus H. Novak; Elias A. Alwan; John L. Volakis
Pages: 557 - 563
Abstract: We present a 60 GHz phased array system that combines several key technologies to realize 10 GHz bandwidth coverage. Particularly, a tightly coupled dipole array centered at 60 GHz is designed and tested for its wideband performance. The tightly coupled dipole elements offer excellent wideband behavior of 10 GHz with voltage standing wave ratio < 3 with scanning to 45°, as well as low cost printed circuit board fabrication. Additionally, we demonstrate a measurement setup with de-embedding procedure to measure gain at the antenna feed point. A feeding structure was designed and fabricated for de-embedding gain pattern measurements. Recovered measurements are shown to be in agreement with simulation.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1295-1
Issue No: Vol. 97, No. 3 (2018)

• A 0.9–5.4 GHz wideband fast settling frequency synthesizer for
5G based consumer services
• Authors: Zaira Zahir; Gaurab Banerjee
Pages: 565 - 577
Abstract: In this paper, a frequency synthesizer, based on a type-2, third order phase locked loop (PLL), covering the frequency range of 0.9–5.4 GHz using three voltage controlled oscillators, is implemented using a 0.13- $$\upmu \hbox {m}$$ CMOS technology. The PLL has three modes of operation—a high bandwidth mode, a low bandwidth mode and a dynamic mode, in which the bandwidth dynamically changes from a low to a high value, during a frequency jump, and reverts back to low value, once the PLL settles. With a proper choice of bandwidth and timing synchronization during a frequency jump, a worst-case settling time of 3- $$\upmu \hbox {s}$$ has been obtained, which is one of the lowest in reported literature. The input clock of the PLL is set to 100 MHz, but it can go as low as 25 MHz without having any effect on its settling time. The PLL consumes 24 mW of power and occupies 0.8 mm $$^2$$ of active area.This PLL is expected to be specially useful in wide-bandwidth cognitive radios that require large and fast transitions in the frequency of operation.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1312-4
Issue No: Vol. 97, No. 3 (2018)

• A standard-blocker tolerant receiver front-end using noise-canceling LNA
with passive N-path filter and variable pulse-width multi-phase clock
generator
Pages: 579 - 591
Abstract: In this paper, input impedance characteristics of N-path filters is used to reject standard blockers at the input port of a receiver front-end. Due to using variable capacitors in the multiphase LO generator, the results of each performance parameter of the design shows a slight change in value at the whole of frequency range. The receiver NF is about 2.45 dB at 1 GHz switching frequency. The proposed receiver front-end is analyzed and is simulated at the schematic level using CMOS 90 nm technology with a 1.5 V supply voltage.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1331-1
Issue No: Vol. 97, No. 3 (2018)

• A novel high dynamic range differential LNA using quartet topology
• Authors: Shahrzad Ajabi; Hooman Kaabi; Karim Ansari-Asl
Pages: 593 - 601
Abstract: In some applications such as short-range radars, a large target can desensitize the receiver. A high dynamic range low-noise amplifier (LNA), as a key component of a transmitter/receiver module, can improve the entire system performance. This study presents a high dynamic range differential LNA that uses a differential quartet topology for the first time. The LNA shows more linearity than the conventional differential common source LNAs. For a typical 0.18 µm CMOS technology, it achieves a power gain of about 5.5 dB at 24 GHz, a low noise figure (NF) of 3.5 dB, very good linearity performance, an input-referred third-order intercept point (IIP3) of + 6.3 dBm, and an input-referred 1 dB compression point (P1dB) of − 4.5 dBm.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1337-8
Issue No: Vol. 97, No. 3 (2018)

• Energy-efficient switching scheme for SAR ADC with only two reference
voltages
• Authors: Shubin Liu; Haolin Han; Ruixue Ding; Zhangming Zhu
Pages: 603 - 613
Abstract: An energy-efficient switching method for successive approximation register analog to digital converter is presented in this letter. The proposed two-step switching scheme using the goblet architecture achieves 99.52% less switching energy and 21.09% area reduction over the conventional switching scheme. Moreover, owing to the application of the goblet architecture, the proposed scheme employs only two reference voltages without any requirements for stability or accuracy of the third voltage level.
PubDate: 2018-12-01
DOI: 10.1007/s10470-018-1339-6
Issue No: Vol. 97, No. 3 (2018)

• Introduction to the special issue on IEEE NEWCAS 2017
• Authors: Morgan Madec; Luc Hebrard; Wilfried Uhring
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1357-4

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