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  Subjects -> ENGINEERING (Total: 1961 journals)
    - CHEMICAL ENGINEERING (153 journals)
    - CIVIL ENGINEERING (149 journals)
    - ELECTRICAL ENGINEERING (81 journals)
    - ENGINEERING (1114 journals)
    - HYDRAULIC ENGINEERING (46 journals)
    - INDUSTRIAL ENGINEERING (52 journals)
    - MECHANICAL ENGINEERING (74 journals)

ENGINEERING (1114 journals)            First | 2 3 4 5 6 7 8 9 | Last

International Journal of Manufacturing Research     Hybrid Journal   (Followers: 6)
International Journal of Manufacturing Technology and Management     Hybrid Journal   (Followers: 8)
International Journal of Materials and Product Technology     Hybrid Journal   (Followers: 4)
International Journal of Mathematical Education in Science and Technology     Hybrid Journal   (Followers: 7)
International Journal of Mathematics in Operational Research     Hybrid Journal   (Followers: 1)
International Journal of Medical Engineering and Informatics     Hybrid Journal   (Followers: 5)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 4)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 1)
International Journal of Microwave Science and Technology     Open Access   (Followers: 2)
International Journal of Mobile Network Design and Innovation     Hybrid Journal   (Followers: 3)
International Journal of Multiphase Flow     Hybrid Journal   (Followers: 2)
International Journal of Nanomanufacturing     Hybrid Journal   (Followers: 1)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Nanotechnology     Hybrid Journal   (Followers: 5)
International Journal of Navigation and Observation     Open Access   (Followers: 5)
International Journal of Network Management     Hybrid Journal  
International Journal of Nonlinear Sciences and Numerical Simulation     Full-text available via subscription   (Followers: 1)
International Journal of Numerical Methods for Heat & Fluid Flow     Hybrid Journal   (Followers: 7)
International Journal of Optics     Open Access   (Followers: 1)
International Journal of Organisational Design and Engineering     Hybrid Journal   (Followers: 9)
International Journal of Pattern Recognition and Artificial Intelligence     Hybrid Journal   (Followers: 6)
International Journal of Pavement Engineering     Hybrid Journal   (Followers: 2)
International Journal of Physical Modelling in Geotechnics     Hybrid Journal   (Followers: 3)
International Journal of Plasticity     Hybrid Journal   (Followers: 6)
International Journal of Plastics Technology     Hybrid Journal  
International Journal of Polymer Analysis and Characterization     Hybrid Journal   (Followers: 4)
International Journal of Polymer Science     Open Access   (Followers: 16)
International Journal of Precision Engineering and Manufacturing     Hybrid Journal   (Followers: 6)
International Journal of Precision Technology     Hybrid Journal  
International Journal of Pressure Vessels and Piping     Hybrid Journal   (Followers: 2)
International Journal of Production Economics     Hybrid Journal   (Followers: 10)
International Journal of Quality and Innovation     Hybrid Journal   (Followers: 3)
International Journal of Quality Engineering and Technology     Hybrid Journal   (Followers: 2)
International Journal of Quantum Information     Hybrid Journal  
International Journal of Rapid Manufacturing     Hybrid Journal   (Followers: 2)
International Journal of Reliability, Quality and Safety Engineering     Hybrid Journal   (Followers: 4)
International Journal of Renewable Energy Technology     Hybrid Journal   (Followers: 8)
International Journal of Robust and Nonlinear Control     Hybrid Journal   (Followers: 2)
International Journal of Science Engineering and Advance Technology     Open Access  
International Journal of Sediment Research     Full-text available via subscription   (Followers: 1)
International Journal of Self-Propagating High-Temperature Synthesis     Hybrid Journal   (Followers: 2)
International Journal of Signal and Imaging Systems Engineering     Hybrid Journal  
International Journal of Six Sigma and Competitive Advantage     Hybrid Journal  
International Journal of Social Robotics     Hybrid Journal   (Followers: 1)
International Journal of Software Engineering and Knowledge Engineering     Hybrid Journal   (Followers: 1)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 2)
International Journal of Speech Technology     Hybrid Journal   (Followers: 3)
International Journal of Spray and Combustion Dynamics     Full-text available via subscription   (Followers: 6)
International Journal of Surface Engineering and Interdisciplinary Materials Science     Full-text available via subscription   (Followers: 1)
International Journal of Surface Science and Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Manufacturing     Hybrid Journal   (Followers: 4)
International Journal of Systems Assurance Engineering and Management     Hybrid Journal  
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 2)
International Journal of Technology Management and Sustainable Development     Hybrid Journal   (Followers: 1)
International Journal of Technology Policy and Law     Hybrid Journal   (Followers: 4)
International Journal of Telemedicine and Applications     Open Access   (Followers: 2)
International Journal of Thermal Sciences     Hybrid Journal   (Followers: 5)
International Journal of Thermodynamics     Open Access   (Followers: 2)
International Journal of Turbo & Jet-Engines     Full-text available via subscription  
International Journal of Ultra Wideband Communications and Systems     Hybrid Journal  
International Journal of Vehicle Autonomous Systems     Hybrid Journal   (Followers: 1)
International Journal of Vehicle Design     Hybrid Journal   (Followers: 6)
International Journal of Vehicle Information and Communication Systems     Hybrid Journal   (Followers: 2)
International Journal of Vehicle Noise and Vibration     Hybrid Journal   (Followers: 3)
International Journal of Vehicle Safety     Hybrid Journal   (Followers: 4)
International Journal of Vehicular Technology     Open Access   (Followers: 2)
International Journal of Virtual Technology and Multimedia     Hybrid Journal   (Followers: 4)
International Journal of Wavelets, Multiresolution and Information Processing     Hybrid Journal  
International Journal on Artificial Intelligence Tools     Hybrid Journal   (Followers: 4)
International Nano Letters     Open Access   (Followers: 6)
International Review of Applied Sciences and Engineering     Full-text available via subscription  
Inverse Problems in Science and Engineering     Hybrid Journal   (Followers: 2)
Ionics     Hybrid Journal  
IPTEK The Journal for Technology and Science     Open Access  
IRBM News     Full-text available via subscription  
Irrigation and Drainage Systems     Hybrid Journal  
ISA Transactions     Full-text available via subscription   (Followers: 1)
ISRN - International Scholarly Research Notices     Open Access   (Followers: 69)
ISRN Nanotechnology     Open Access  
ISRN Signal Processing     Open Access  
ISRN Thermodynamics     Open Access  
IT Professional     Full-text available via subscription   (Followers: 3)
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 1)
Journal of Advanced Manufacturing Systems     Hybrid Journal   (Followers: 7)
Journal of Aerosol Science     Hybrid Journal   (Followers: 2)
Journal of Aerospace Engineering     Full-text available via subscription   (Followers: 144)
Journal of Alloys and Compounds     Hybrid Journal   (Followers: 7)
Journal of Analytical and Applied Pyrolysis     Hybrid Journal   (Followers: 3)
Journal of Analytical Science & Technology     Open Access   (Followers: 4)
Journal of Analytical Sciences, Methods and Instrumentation     Open Access   (Followers: 1)
Journal of Applied Analysis     Full-text available via subscription  
Journal of Applied and Industrial Sciences     Open Access  
Journal of Applied Logic     Full-text available via subscription  
Journal of Applied Physics     Hybrid Journal   (Followers: 168)
Journal of Applied Probability     Full-text available via subscription   (Followers: 6)
Journal of Applied Research and Technology     Open Access  
Journal of Applied Science and Technology     Full-text available via subscription  
Journal of Applied Sciences     Open Access   (Followers: 5)
Journal of Architectural Engineering     Full-text available via subscription   (Followers: 6)

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Journal Cover Journal of Electronic Testing
   Journal TOC RSS feeds Export to Zotero [3 followers]  Follow    
   Hybrid Journal Hybrid journal (It can contain Open Access articles)
     ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
     Published by Springer-Verlag Homepage  [2209 journals]   [SJR: 0.424]   [H-I: 22]
  • On the Test and Mitigation of Malfunctions in Low-Power SRAMs
    • Abstract: Abstract In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, address decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.
      PubDate: 2014-10-05
  • Editorial
    • PubDate: 2014-10-02
  • Adaptive Bayesian Diagnosis of Intermittent Faults
    • Abstract: Abstract With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some intermediate signatures during embedded test or built-in self-test. Permanent faults are easily determined by repeating test sessions. Intermittent and transient faults can be identified by the amount of failing test sessions in many cases. For the remaining faults, a Bayesian classification technique has been developed which is applicable to large digital circuits. The combination of these methods is able to identify intermittent faults with a probability of more than 98 %.
      PubDate: 2014-09-30
  • Efficient LFSR Reseeding Based on Internal-Response Feedback
    • Abstract: Abstract LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
      PubDate: 2014-09-30
  • Intra-Cell Defects Diagnosis
    • Abstract: Abstract The diagnosis is the process of isolating possible sources of observed failures in a defective circuit. Today, manufacturing defects appear not only in the cell interconnection, but also inside the cell itself (intra-cell defect). State of the art diagnosis approaches can identify the defect location at gate level (i.e., one or more standard cells and/or inter-connections can be provided as possible defect location). Some approaches have been developed to target the intra-cell defects. In this paper, we propose an intra-cell diagnosis method based on the “Effect-Cause” paradigm aiming at locating the root cause of the observed failures inside a logic cell. It is based on the Critical Path Tracing (CPT) here applied at transistor level. The main characteristic of our approach is that it exploits the analysis of the faulty behavior induced by the actual defect. In other word, we locate the defect by simply analyzing the effect induced by the defect itself. The advantage is the fact that we are defect independent (i.e., we do not have to explicitly consider the type and the size of the defect). Moreover, since the complexity of a single cell in terms of transistor number is low, the proposed intra-cell diagnosis approach requires a negligible computational time. The efficiency of the proposed approach has been evaluated by means of experimental results carried out on both simulations-based and industrial silicon data case studies.
      PubDate: 2014-09-30
  • Fault Diagnosis of Analog Circuit Based on High-Order Cumulants and
           Information Fusion
    • Abstract: Abstract This paper proposes a method of analog circuit fault diagnosis by using high-order cumulants and information fusion. We extract the original voltage and current signals from output terminal of the circuit under test, and determine corresponding kurtosis and skewness as fault eigenvectors, which are then used to improve Error Back Propagation (BP) neural network for fault diagnosis. With respect to fault eigenvectors consider more about the information which are sometimes ignored by principal component analysis (PCA) using second order statistics. By employing information fusion to integrate voltage with current as fault eigenvectors, eigenvectors can be used to express fault information better. Diagnosis examples are used to illustrate that our fault eigenvectors own higher recognition rate and diagnosis accuracy.
      PubDate: 2014-09-27
  • Test Technology Newsletter
    • PubDate: 2014-09-23
  • A New Analytical Model of SET Latching Probability for Circuits
           Experiencing Single- or Multiple-Cycle Single-Event Transients
    • Abstract: Abstract As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.
      PubDate: 2014-09-23
  • Optimal Test Scheduling Formulation under Power Constraints with Dynamic
           Voltage and Frequency Scaling
    • Abstract: Abstract As a consequence of technology scaling and increasing power consumption of modern high performance designs, various techniques, such as clock gating and Dynamic Voltage and Frequency Scaling (DVFS), have been adapted to address power issues. These techniques are important and desirable to address reliability needs as well as economic issues. From a testing point of view, the introduction of power constraints during testing is needed to achieve the desired product quality and to avoid yield loss. Unlike designers who have benefited from the Design-for-Test hardware introduced for testing, test engineers have rarely taken advantage of the extra hardware introduced to meet design needs. In this paper, we make use of the DVFS technology and its associated hardware to improve test economics. We formulate the power constrained testing problem as an optimization problem that makes use of DVFS technology. We show that superior test schedules can be obtained for both session-based and sessionless testing methods relative to existing and traditional methods of obtaining test schedules.
      PubDate: 2014-09-21
  • Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters
    • Abstract: Abstract Phase-locked loops (PLLs) serve as core building blocks for communication systems and are often used to synthesize IO clocks for data synchronization and frequency sources for RF conversion. Testing of PLL loop performance is consequently important for guaranteeing the reliability of the underlying communication systems. In this paper, a low cost testing method based on loop triggering and use of built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learning is applied to predict the required PLL parameters from the observed sensor response after “training”. In order to verify analog sensor testing in PLL loop response evaluation, an off-the-shelf PLL and a PLL on printed circuit board (PCB) are tested using this method. The results are analyzed and shown with high correlation to loop parameters. Parameters including charge pump current, voltage-controlled oscillator (VCO) gain, bandwidth, phase margin, and locking time are predicted accurately to prove the viability of the proposed test method.
      PubDate: 2014-09-20
  • Testing Methods for PUF-Based Secure Key Storage Circuits
    • Abstract: Abstract Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. It investigates two secure Built-In Self-Test (BIST) solutions for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The schemes target high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The first scheme reuses existing FE blocks (for pattern generation and compression) to minimize the area overhead, while the second scheme tests all the FE blocks simultaneously to minimize the test time. The schemes are integrated in FE design and simulated; the results show that for the first test scheme, a SAF fault coverage of 95 % can be realized with no more than 47.1k clock cycles at the cost of a negligible area overhead of only 2.2 %; while for the second test scheme a SAF fault coverage of 95 % can be realized with 3.5k clock cycles at the cost of 18.6 % area overhead. Higher fault coverages are possible to realize at extra cost (i.e., either by extending the test time, or by adding extra hardware, or a combination of both).
      PubDate: 2014-09-17
  • Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs
    • Abstract: Abstract In data acquisition systems, with help of time-interleaved analog-to-digital converter (TIADC) architecture, the maximum sample rate of the whole system can be increased efficiently. However, inevitable offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the sampling performance. In order to develop the mismatched TIADC structure, this paper first proposes a new time-domain algorithm to estimate the three aforementioned mismatch errors, and then puts forward a calibration method to calibrate the mismatch errors. Finally, numerical simulations are presented to verify the proposed estimation and calibration algorithm.
      PubDate: 2014-09-07
  • Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets
    • Abstract: Abstract Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.
      PubDate: 2014-09-06
  • Dynamic Threshold Delay Characterization Model for Improved Static Timing
    • Abstract: Abstract Transistors within a gate take a finite amount of time to switch and hence there is always a propagation delay associated with it. These delays are evaluated by standard cell characterization techniques using EDA tools. However, these standard measurement methods tend to fail when simulating the design with practical values of slope and load and gives rise to the problem of negative or non-monotonic delays. Negative/non-monotonic delays lead to false positives during static timing analysis, synthesis and simulation of circuits and are undesirable. Hence, there is a need to implement new methods for characterization of propagation delay that will lead to more realistic monotonic delay values, ultimately achieving early timing closures. One such method of delay measurement based on actual switching thresholds has been proposed in this work.
      PubDate: 2014-08-16
  • Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal
    • Abstract: Abstract This paper introduces a new fault diagnosis strategy for analog circuits based on conic optimization and ellipsoidal classifiers. Ellipsoidal classifiers are trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the output of the ellipsoidal classifiers is used to isolate the actual CUT fault. The constructed classifiers exhibit high classification rate with competitive computational complexity even if the CUT has overlapping faults. Experimental results demonstrate the superior performance of the ellipsoidal classifiers in analog fault diagnosis.
      PubDate: 2014-08-15
  • Fault Detection of Linear Analog Integrated Circuit in Network
    • Abstract: Abstract This paper presents a novel network decomposition method that can detect faults of linear analog integrated circuit (IC) in network. The nodal admittance matrix (NAM) of linear analog IC is a function of its internal component values, which can be used for fault detection. However, it is difficult to obtain the NAM of linear analog IC in network. We propose a network decomposition based method to calculate the NAM of the IC under test in network. The IC under test is fault free, if its NAM lies inside the tolerance limit. Otherwise, it is faulty. The effectiveness of the proposed method is validated through benchmark circuits.
      PubDate: 2014-07-29
  • Editorial
    • PubDate: 2014-07-25
  • Test Technology Newsletter
    • PubDate: 2014-07-23
  • A Functional Approach for Testing the Reorder Buffer Memory
    • Abstract: Abstract Superscalar processors have the ability to execute instructions out-of-order to better exploit the internal hardware and to maximize the performance. To maintain the in-order instruction commitment and to guarantee the correctness of the final results (as well as precise exception management), the Reorder Buffer (ROB) may be used. From the architectural point of view, the ROB is a memory array of several thousands of bits that must be tested against hardware faults to ensure a correct behavior of the processor. Since it is deeply embedded within the microprocessor circuitry, the most straightforward approach to test the ROB is through Built-In Self-Test solutions, which are typically adopted by manufacturers for end-of-production test. However, these solutions may not always be used for the test during the operational phase (in-field test) which aims at detecting possible hardware faults arising when the electronic systems works in its target environment. In fact, these solutions require the usage of test infrastructures that may not be accessible and/or documented, or simply not usable during the operational phase. This paper proposes an alternative solution, based on a functional approach, in which the test is performed by forcing the processor to execute a specially written test program, and checking the resulting behavior of the processor. This approach can be adopted for in-field test, e.g., at the power-on, power-off, or during the time slots unused by the system application. The method has been validated resorting to both an architectural and a memory fault simulator.
      PubDate: 2014-06-15
  • A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and
    • Abstract: Abstract This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS’85 and ITC’99 benchmark circuits show that our approach has an area cost of about 3 % to 6 % with a power consumption saving of about 33 % compared to TMR architectures.
      PubDate: 2014-06-08
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