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Journal of Electronic Testing

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ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
Published by Springer-Verlag

[2216 journals]

A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic
- Abstract: Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.
  PubDate: 2013-05-12
A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip
- Abstract: This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.
  PubDate: 2013-05-03
Process-Variation and Temperature Aware SoC Test Scheduling Technique
- Abstract: High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC’02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.
  PubDate: 2013-05-01
Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems
- Abstract: This paper presents a novel approach to the design of multi-/many-core systems with an adaptive level of reliability. The approach defines a layer at the operating system level that achieves fault detection/tolerance/diagnosis properties by means of thread replication and re-execution mechanisms. The layer applies the most convenient hardening mechanism to achieve the desired trade-off between reliability and performance by adapting at run-time to the changes of the working scenario. The proposed strategy has been applied in a set of experimental sessions considering a real-world parallel application, to evaluate its benefits on the final system with respect to various strategies selected at design time.
  PubDate: 2013-04-17
Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks
- Abstract: A new method to identify component faults in analog circuits is proposed using network parameters like driving point impedance, transfer impedance, voltage gain and current gain. Using Monte-Carlo simulation each component of the circuit is varied within its tolerance limit and samples of each network parameter are found for fault free circuit. Similarly all possible single faults are introduced and the corresponding samples of network parameters are found. Fault classification is done through neural network. The proposed method is validated through second order Sallenkey band pass filter. Numerical results are presented to clarify the proposed method and prove its efficiency.
  PubDate: 2013-04-11
On the Simulation of HCI-Induced Variations of IC Timings at High Level
- Abstract: Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths.
  PubDate: 2013-04-11
Circuit Level Concurrent Error Detection in FSMs
- Abstract: Finite state machines (FSMs) are contained in many building blocks of digital electronic circuits. Such electronic circuits are prone to transient errors, caused e.g. by cosmic radiation, and to permanent errors. In this article, the authors give an overview of known error detection methods for FSMs. One method (dependent state encoding for dynamic error detection) is described in detail, as well as the problems arising when the method is applied to a practical example. Additionally, the authors propose a modification of the method above. For several benchmark circuits, this modification shows better results, compared to the state-of-the-art implementation.
  PubDate: 2013-04-07
Editorial
- PubDate: 2013-04-06
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design
- Abstract: Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. This paper addresses this problem using an integer linear programming (ILP) approach. Specifically, on a heterogeneous 3D CMP, it explores how applications can be mapped onto 3D ICs to maximize reliability. Preliminary experiments indicate that the proposed technique generates promising results in both reliability and performance.
  PubDate: 2013-04-04
Guest Editorial
- PubDate: 2013-04-02
Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems
- Abstract: Several criteria can be used to evaluate the criticality of registers and memory locations at compile time. This evaluation is useful to guide optimizations with respect to robustness constraints and soft error mitigation. In this paper, we analyze in detail the impact of compilation optimizations on the system dependability, using four different criteria. We show that optimizations enabled by default lead to criticality increase. However, selectively picking optimizations may increase the robustness of a system even if the consequences of a given optimization option may vary from a program to another. We also identify some optimizations that induce a significant increase in criticality and must be used with care.
  PubDate: 2013-04-02
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
- Abstract: Due to the continuous technology scaling, soft error becomes a major reliability issue at nanoscale technologies. Single or multiple event transients at low levels can result in multiple correlated bit flips at logic or higher abstraction levels. Addressing this correlation is essential for accurate low-level soft error rate estimation, and more importantly, for the cross-level error abstraction, e.g. from bit errors at logic level to word errors at register-transfer level. This paper proposes a novel error estimation method to take into consideration both signal and error correlations. It unifies the treatment of error-free signals and erroneous signals, so that the computation of error probabilities and correlations can be carried out using techniques for signal probabilities and correlations calculation. The proposed method not only reports accurate error probabilities when internal gates are impaired by soft errors, but also gives quantification of the error correlations in their propagation process. This feature enables our method to be a versatile technique used in high-level error estimation. The experimental results validate our proposed technique showing that compared with Monte-Carlo simulation, it is 5 orders of magnitude faster, while the average inaccuracy of error probability estimation is only 0.02.
  PubDate: 2013-04-02
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor
- Abstract: True Random Number Generators have many uses, in particular they play a key role in security applications and cryptographic algorithms. Our interest lies in the quality of their generated random numbers. More specifically, for such utilizations, a slight deviation of the numbers from a “perfect” behavior can have disastrous consequences. It is then necessary to devise schemes for the testing of these generators in order to detect non-random properties of their numbers. Moreover, one should consider them from an attacker point of view and use any means to try to perturbate their good functionnality. In this article we describe such experiments and several standard statistical tools for the generators testing. We also present experimental results obtained through the study of a generator embedded in a processor in order to illustrate our methodology. We show that its pertubation leads to the apparition of dangerous deviations in its numbers distribution.
  PubDate: 2013-03-27
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
- Abstract: The constant pressure for making functional verification more agile has led to the conception of coverage driven verification (CDV) techniques. CDV has been implemented in verification testbenches using supervised learning techniques to model the relationship between coverage events and stimuli generation, providing a feedback between them. One commonly used technique is the classification- or decision-tree data mining, which has shown to be appropriate due to the easy modeling. Learning techniques are applied in two steps: training and application. Training is made on one or more sets of examples, which relate datasets to pre-determined classes. Precision of results by applying the predictive learning concept has shown to be sensitive to the size of the training set and the amount of imbalance of associated classes, this last meaning the number of datasets associated to each class is very different from each other. This work presents experiments on the manipulation of data mining training sets, by changing the size and reducing the imbalances, in order to check their influence on the CDV efficiency. To do that, a circuit example with a large input space and strong class imbalance was selected from the application domain of multimedia systems and another one, with a small input space that affects the coverage occurrences, was selected from the communication area.
  PubDate: 2013-03-27
Secure JTAG Implementation Using Schnorr Protocol
- Abstract: The standard IEEE 1149.1 (Test Access Port and Boundary-Scan Architecture, also known as JTAG port) provides a useful interface for embedded systems development, debug, and test. In an 1149.1-compatible integrated circuit, the JTAG port allows the circuit to be easily accessed from the external world, and even to control and observe the internal scan chains of the circuit. However, the JTAG port can be also exploited by attackers to mount several cryptographic attacks. In this paper we propose a novel architecture that implements a secure JTAG interface. Our JTAG scheme allows for mutual authentication between the device and the tester. In contrast to previous work, our scheme uses provably secure asymmetric-key based authentication and verification protocols. The complete scheme is implemented in hardware and integrated with the standard JTAG interface. Detailed area and timing results are also presented.
  PubDate: 2013-03-24
Test Technology Newsletter
- PubDate: 2013-03-21
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
- Abstract: In recent work, the error latching probability due to an SET is calculated for a single observable point, and this help in hardening the design. This paper utilizes a recently proposed probabilistic framework for SET propagation in order to diagnose the location and time of strike based on errors observed at multiple points. The proposed diagnostic framework requires a new approach to calculate the probability for SET propagation to multiple non-independent variables. It is shown experimentally that error appearances at multiple observable points help in SET diagnosis. The time performance of the proposed diagnostic framework is compared against an alternative implementation. This is particularly important in on-line diagnosis.
  PubDate: 2013-03-21
On the Impact of Performance Faults in Modern Microprocessors
- Abstract: Modern microprocessors incorporate a variety of architectural features, such as branch prediction and speculative execution, which are not critical to the correctness of their operation yet are essential towards improving performance. Accordingly, while faults in the corresponding hardware may not necessarily affect functional correctness, they may, nevertheless, adversely impact performance. In this paper, we investigate quantitatively the performance impact of such faults using a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks. We provide extensive fault simulation-based experimental results that elucidate the various aspects of performance faults and we discuss how this information may guide the inclusion of additional hardware for performance loss recovery and yield enhancement.
  PubDate: 2013-03-21
A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients
- Abstract: A novel built-in voltage sensor circuit has been developed in 90-nm CMOS technology to characterize temporal and physical locations of ion hits. The sensing circuit only has 8 transistors, with very small area and power overhead. Simulations and laser experimental results illustrate the effectiveness of the sensing circuit. The sensors can be implemented in grid formation to systematically detect the ion hits in real time.
  PubDate: 2013-03-20
Novel Self-Timed, Pipelined Clock Scan Architecture
- Abstract: In this paper, we describe a novel self-timed scan chain design approach to mitigate hold time and power supply noise problems during scan testing, and to simultaneously allow no delay penalty due to the front-end multiplexer in a multiplexer-D flip-flop (mux-DFF) scan cell. Hold time problems due to clock skew and static and dynamic power supply noise (i.e. IR drop and LdI/dt noise) due to simultaneous switching are two problems associated with shift operations during scan testing using ATPG patterns. These problems are particularly serious with mux-DFF style scan, and are either nonexistent or negligible with level-sensitive scan design (LSSD). This paper deals with a circuit technique to mitigate hold time, power supply noise and front-end delay penalty seen with mux-DFF and achieve a middle ground on clock routing overhead between LSSD and mux-DFF scan styles.
  PubDate: 2013-03-06