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  Subjects -> ENGINEERING (Total: 1955 journals)
    - CHEMICAL ENGINEERING (153 journals)
    - CIVIL ENGINEERING (148 journals)
    - ELECTRICAL ENGINEERING (82 journals)
    - ENGINEERING (1111 journals)
    - HYDRAULIC ENGINEERING (45 journals)
    - INDUSTRIAL ENGINEERING (52 journals)
    - MECHANICAL ENGINEERING (74 journals)

ENGINEERING (1111 journals)            First | 2 3 4 5 6 7 8 9 | Last

International Journal of Manufacturing Technology and Management     Hybrid Journal   (Followers: 8)
International Journal of Materials and Product Technology     Hybrid Journal   (Followers: 4)
International Journal of Mathematical Education in Science and Technology     Hybrid Journal   (Followers: 6)
International Journal of Mathematics in Operational Research     Hybrid Journal   (Followers: 1)
International Journal of Medical Engineering and Informatics     Hybrid Journal   (Followers: 5)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 3)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 1)
International Journal of Microwave Science and Technology     Open Access   (Followers: 2)
International Journal of Mobile Network Design and Innovation     Hybrid Journal   (Followers: 3)
International Journal of Multiphase Flow     Hybrid Journal   (Followers: 2)
International Journal of Nanomanufacturing     Hybrid Journal   (Followers: 1)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Nanotechnology     Hybrid Journal   (Followers: 5)
International Journal of Navigation and Observation     Open Access   (Followers: 5)
International Journal of Network Management     Hybrid Journal  
International Journal of Nonlinear Sciences and Numerical Simulation     Full-text available via subscription   (Followers: 1)
International Journal of Numerical Methods for Heat & Fluid Flow     Hybrid Journal   (Followers: 7)
International Journal of Optics     Open Access   (Followers: 1)
International Journal of Organisational Design and Engineering     Hybrid Journal   (Followers: 8)
International Journal of Pattern Recognition and Artificial Intelligence     Hybrid Journal   (Followers: 6)
International Journal of Pavement Engineering     Hybrid Journal   (Followers: 2)
International Journal of Physical Modelling in Geotechnics     Hybrid Journal   (Followers: 3)
International Journal of Plasticity     Hybrid Journal   (Followers: 6)
International Journal of Plastics Technology     Hybrid Journal  
International Journal of Polymer Analysis and Characterization     Hybrid Journal   (Followers: 3)
International Journal of Polymer Science     Open Access   (Followers: 16)
International Journal of Precision Engineering and Manufacturing     Hybrid Journal   (Followers: 6)
International Journal of Precision Technology     Hybrid Journal  
International Journal of Pressure Vessels and Piping     Hybrid Journal   (Followers: 2)
International Journal of Production Economics     Hybrid Journal   (Followers: 10)
International Journal of Quality and Innovation     Hybrid Journal   (Followers: 3)
International Journal of Quality Engineering and Technology     Hybrid Journal   (Followers: 2)
International Journal of Quantum Information     Hybrid Journal  
International Journal of Rapid Manufacturing     Hybrid Journal   (Followers: 2)
International Journal of Reliability, Quality and Safety Engineering     Hybrid Journal   (Followers: 4)
International Journal of Renewable Energy Technology     Hybrid Journal   (Followers: 7)
International Journal of Robust and Nonlinear Control     Hybrid Journal   (Followers: 2)
International Journal of Science Engineering and Advance Technology     Open Access  
International Journal of Sediment Research     Full-text available via subscription   (Followers: 1)
International Journal of Self-Propagating High-Temperature Synthesis     Hybrid Journal   (Followers: 2)
International Journal of Signal and Imaging Systems Engineering     Hybrid Journal  
International Journal of Six Sigma and Competitive Advantage     Hybrid Journal  
International Journal of Social Robotics     Hybrid Journal   (Followers: 1)
International Journal of Software Engineering and Knowledge Engineering     Hybrid Journal   (Followers: 1)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 2)
International Journal of Speech Technology     Hybrid Journal   (Followers: 3)
International Journal of Spray and Combustion Dynamics     Full-text available via subscription   (Followers: 6)
International Journal of Surface Engineering and Interdisciplinary Materials Science     Full-text available via subscription   (Followers: 1)
International Journal of Surface Science and Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Manufacturing     Hybrid Journal   (Followers: 4)
International Journal of Systems Assurance Engineering and Management     Hybrid Journal  
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 2)
International Journal of Technology Management and Sustainable Development     Hybrid Journal   (Followers: 1)
International Journal of Technology Policy and Law     Hybrid Journal   (Followers: 4)
International Journal of Telemedicine and Applications     Open Access   (Followers: 2)
International Journal of Thermal Sciences     Hybrid Journal   (Followers: 4)
International Journal of Thermodynamics     Open Access   (Followers: 1)
International Journal of Turbo & Jet-Engines     Full-text available via subscription  
International Journal of Ultra Wideband Communications and Systems     Hybrid Journal  
International Journal of Vehicle Autonomous Systems     Hybrid Journal   (Followers: 1)
International Journal of Vehicle Design     Hybrid Journal   (Followers: 6)
International Journal of Vehicle Information and Communication Systems     Hybrid Journal   (Followers: 2)
International Journal of Vehicle Noise and Vibration     Hybrid Journal   (Followers: 3)
International Journal of Vehicle Safety     Hybrid Journal   (Followers: 4)
International Journal of Vehicular Technology     Open Access   (Followers: 2)
International Journal of Virtual Technology and Multimedia     Hybrid Journal   (Followers: 4)
International Journal of Wavelets, Multiresolution and Information Processing     Hybrid Journal  
International Journal on Artificial Intelligence Tools     Hybrid Journal   (Followers: 4)
International Nano Letters     Open Access   (Followers: 6)
International Review of Applied Sciences and Engineering     Full-text available via subscription  
Inverse Problems in Science and Engineering     Hybrid Journal   (Followers: 2)
Ionics     Hybrid Journal  
IPTEK The Journal for Technology and Science     Open Access  
IRBM News     Full-text available via subscription  
Irrigation and Drainage Systems     Hybrid Journal  
ISA Transactions     Full-text available via subscription   (Followers: 1)
ISRN - International Scholarly Research Notices     Open Access   (Followers: 69)
ISRN Nanotechnology     Open Access  
ISRN Signal Processing     Open Access  
ISRN Thermodynamics     Open Access  
IT Professional     Full-text available via subscription   (Followers: 2)
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 1)
Journal of Advanced Manufacturing Systems     Hybrid Journal   (Followers: 7)
Journal of Aerosol Science     Hybrid Journal   (Followers: 2)
Journal of Aerospace Engineering     Full-text available via subscription   (Followers: 131)
Journal of Alloys and Compounds     Hybrid Journal   (Followers: 7)
Journal of Analytical and Applied Pyrolysis     Hybrid Journal   (Followers: 3)
Journal of Analytical Science & Technology     Open Access   (Followers: 4)
Journal of Analytical Sciences, Methods and Instrumentation     Open Access   (Followers: 1)
Journal of Applied Analysis     Full-text available via subscription  
Journal of Applied and Industrial Sciences     Open Access  
Journal of Applied Logic     Full-text available via subscription  
Journal of Applied Physics     Hybrid Journal   (Followers: 161)
Journal of Applied Probability     Full-text available via subscription   (Followers: 6)
Journal of Applied Research and Technology     Open Access  
Journal of Applied Science and Technology     Full-text available via subscription  
Journal of Applied Sciences     Open Access   (Followers: 5)
Journal of Architectural Engineering     Full-text available via subscription   (Followers: 5)
Journal of ASTM International     Full-text available via subscription   (Followers: 3)

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Journal Cover Journal of Electronic Testing
   Journal TOC RSS feeds Export to Zotero [3 followers]  Follow    
   Hybrid Journal Hybrid journal (It can contain Open Access articles)
     ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
     Published by Springer-Verlag Homepage  [2210 journals]   [SJR: 0.424]   [H-I: 22]
  • Optimal Test Scheduling Formulation under Power Constraints with Dynamic
           Voltage and Frequency Scaling
    • Abstract: Abstract As a consequence of technology scaling and increasing power consumption of modern high performance designs, various techniques, such as clock gating and Dynamic Voltage and Frequency Scaling (DVFS), have been adapted to address power issues. These techniques are important and desirable to address reliability needs as well as economic issues. From a testing point of view, the introduction of power constraints during testing is needed to achieve the desired product quality and to avoid yield loss. Unlike designers who have benefited from the Design-for-Test hardware introduced for testing, test engineers have rarely taken advantage of the extra hardware introduced to meet design needs. In this paper, we make use of the DVFS technology and its associated hardware to improve test economics. We formulate the power constrained testing problem as an optimization problem that makes use of DVFS technology. We show that superior test schedules can be obtained for both session-based and sessionless testing methods relative to existing and traditional methods of obtaining test schedules.
      PubDate: 2014-09-21
  • Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters
    • Abstract: Abstract Phase-locked loops (PLLs) serve as core building blocks for communication systems and are often used to synthesize IO clocks for data synchronization and frequency sources for RF conversion. Testing of PLL loop performance is consequently important for guaranteeing the reliability of the underlying communication systems. In this paper, a low cost testing method based on loop triggering and use of built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learning is applied to predict the required PLL parameters from the observed sensor response after “training”. In order to verify analog sensor testing in PLL loop response evaluation, an off-the-shelf PLL and a PLL on printed circuit board (PCB) are tested using this method. The results are analyzed and shown with high correlation to loop parameters. Parameters including charge pump current, voltage-controlled oscillator (VCO) gain, bandwidth, phase margin, and locking time are predicted accurately to prove the viability of the proposed test method.
      PubDate: 2014-09-20
  • Testing Methods for PUF-Based Secure Key Storage Circuits
    • Abstract: Abstract Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. It investigates two secure Built-In Self-Test (BIST) solutions for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The schemes target high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The first scheme reuses existing FE blocks (for pattern generation and compression) to minimize the area overhead, while the second scheme tests all the FE blocks simultaneously to minimize the test time. The schemes are integrated in FE design and simulated; the results show that for the first test scheme, a SAF fault coverage of 95 % can be realized with no more than 47.1k clock cycles at the cost of a negligible area overhead of only 2.2 %; while for the second test scheme a SAF fault coverage of 95 % can be realized with 3.5k clock cycles at the cost of 18.6 % area overhead. Higher fault coverages are possible to realize at extra cost (i.e., either by extending the test time, or by adding extra hardware, or a combination of both).
      PubDate: 2014-09-17
  • Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs
    • Abstract: Abstract In data acquisition systems, with help of time-interleaved analog-to-digital converter (TIADC) architecture, the maximum sample rate of the whole system can be increased efficiently. However, inevitable offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the sampling performance. In order to develop the mismatched TIADC structure, this paper first proposes a new time-domain algorithm to estimate the three aforementioned mismatch errors, and then puts forward a calibration method to calibrate the mismatch errors. Finally, numerical simulations are presented to verify the proposed estimation and calibration algorithm.
      PubDate: 2014-09-07
  • Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets
    • Abstract: Abstract Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.
      PubDate: 2014-09-06
  • Dynamic Threshold Delay Characterization Model for Improved Static Timing
    • Abstract: Abstract Transistors within a gate take a finite amount of time to switch and hence there is always a propagation delay associated with it. These delays are evaluated by standard cell characterization techniques using EDA tools. However, these standard measurement methods tend to fail when simulating the design with practical values of slope and load and gives rise to the problem of negative or non-monotonic delays. Negative/non-monotonic delays lead to false positives during static timing analysis, synthesis and simulation of circuits and are undesirable. Hence, there is a need to implement new methods for characterization of propagation delay that will lead to more realistic monotonic delay values, ultimately achieving early timing closures. One such method of delay measurement based on actual switching thresholds has been proposed in this work.
      PubDate: 2014-08-16
  • Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal
    • Abstract: Abstract This paper introduces a new fault diagnosis strategy for analog circuits based on conic optimization and ellipsoidal classifiers. Ellipsoidal classifiers are trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the output of the ellipsoidal classifiers is used to isolate the actual CUT fault. The constructed classifiers exhibit high classification rate with competitive computational complexity even if the CUT has overlapping faults. Experimental results demonstrate the superior performance of the ellipsoidal classifiers in analog fault diagnosis.
      PubDate: 2014-08-15
  • An Accurate Combination of on-the-fly Interface Trap and Threshold Voltage
           Methods for NBTI Degradation Extraction
    • Abstract: Abstract The Negative bias temperature instability (NBTI) is one of the most important reliability issues for modern CMOS technology. Accurate reliability prediction necessitates physically based models for NBTI and accurate methods for estimation of interface (∆N it ) and oxide trap (∆N ot ) generated under this degradation as well as mobility degradation (∆μ eff /μ eff0 ). In this paper, we propose an accurate approach to estimate ∆N it , ∆N ot and ∆μ eff /μ eff0 induced by NBTI degradation. This approach is based on combining on-the-fly interface trap (OTFIT) and on-the-fly threshold voltage (OTF-Vth) methods in the same time measurement setup, contrary to the classical combination where the two methods (OTFIT and OTF-Vth) are applied separately in two different measurements setups and using two transistors. In addition, the contribution of border trap to the charge pumping (CP) current in OTFIT is minimized using the high frequency signal and the scan band energy of the two combined methods is calibrated. Therefore, the data set of OTFIT and OTF-Vth can be directly comparable. The proposed approach can contribute to further understand the behavior of the NBTI degradation, especially through the mobility degradation and the threshold voltage shift contributions of interface (∆V it ) and oxide traps (∆V ot ).
      PubDate: 2014-08-01
  • Fault Detection of Linear Analog Integrated Circuit in Network
    • Abstract: Abstract This paper presents a novel network decomposition method that can detect faults of linear analog integrated circuit (IC) in network. The nodal admittance matrix (NAM) of linear analog IC is a function of its internal component values, which can be used for fault detection. However, it is difficult to obtain the NAM of linear analog IC in network. We propose a network decomposition based method to calculate the NAM of the IC under test in network. The IC under test is fault free, if its NAM lies inside the tolerance limit. Otherwise, it is faulty. The effectiveness of the proposed method is validated through benchmark circuits.
      PubDate: 2014-07-29
  • Editorial
    • PubDate: 2014-07-25
  • Enhanced Low Complex Double Error Correction Coding with Crosstalk
           Avoidance for Reliable On-Chip Interconnection Link
    • Abstract: Abstract As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link.
      PubDate: 2014-07-25
  • Test Technology Newsletter
    • PubDate: 2014-07-23
  • Recovery Time and Fault Tolerance Improvement for Circuits mapped on
           SRAM-based FPGAs
    • Abstract: Abstract The rapid adoption of FPGA-based systems in space and avionics demands dependability rules from the design to the layout phases to protect against radiation effects. Triple Modular Redundancy is a widely used fault tolerance methodology to protect circuits against radiation-induced Single Event Upsets implemented on SRAM-based FPGAs. The accumulation of SEUs in the configuration memory can cause the TMR replicas to fail, requiring a periodic write-back of the configuration bit-stream. The associated system downtime due to scrubbing and the probability of simultaneous failures of two TMR domains are increasing with growing device densities. We propose a methodology to reduce the recovery time of TMR circuits with increased resilience to Cross-Domain Errors. Our methodology consists of an automated tool-flow for fine-grain error detection, error flags convergence and non-overlapping domain placement. The fine-grain error detection logic identifies the faulty domain using gate-level functions while the error flag convergence logic reduces the overwhelming number of flag signals. The non-overlapping placement enables selective domain reconfiguration and greatly reduces the number of Cross-Domain Errors. Our results demonstrate an evident reduction of the recovery time due to fast error detection time and selective partial reconfiguration of faulty domains. Moreover, the methodology drastically reduces Cross-Domain Errors in Look-Up Tables and routing resources. The improvements in recovery time and fault tolerance are achieved at an area overhead of a single LUT per majority voter in TMR circuits.
      PubDate: 2014-07-12
  • The Use of Software Engineering Methods for Efficacious Test Program
           Creation: A Supportive Evidence Based Case Study
    • Abstract: Abstract Within the semiconductor manufacturing chain the automated testing steps are coming increasingly into focus. Delivering enhanced functionality per IC is expected, with the costs per die being reduced, while, at the same time, the costs of semiconductor electrical tests increase disproportionately. In addition, the requirements for quality are significantly growing, in general, and in particular, being ensured by automated testing. Hence, the execution of test development and test method quality are becoming an important, competitive-advantage topic. This paper presents a case study that evidences such advantage by adopting software engineering methodologies in test program generation. A software cost model applied to test program development parameters, assessed in combination with Bayesian analysis and Gaussian statistical methods, is discussed in detail. Furthermore, the results obtained indicate the effectiveness of the proposed approach, evidencing a remarkable effort reduction, and address quality robustness in semiconductor test engineering.
      PubDate: 2014-06-18
  • A Functional Approach for Testing the Reorder Buffer Memory
    • Abstract: Abstract Superscalar processors have the ability to execute instructions out-of-order to better exploit the internal hardware and to maximize the performance. To maintain the in-order instruction commitment and to guarantee the correctness of the final results (as well as precise exception management), the Reorder Buffer (ROB) may be used. From the architectural point of view, the ROB is a memory array of several thousands of bits that must be tested against hardware faults to ensure a correct behavior of the processor. Since it is deeply embedded within the microprocessor circuitry, the most straightforward approach to test the ROB is through Built-In Self-Test solutions, which are typically adopted by manufacturers for end-of-production test. However, these solutions may not always be used for the test during the operational phase (in-field test) which aims at detecting possible hardware faults arising when the electronic systems works in its target environment. In fact, these solutions require the usage of test infrastructures that may not be accessible and/or documented, or simply not usable during the operational phase. This paper proposes an alternative solution, based on a functional approach, in which the test is performed by forcing the processor to execute a specially written test program, and checking the resulting behavior of the processor. This approach can be adopted for in-field test, e.g., at the power-on, power-off, or during the time slots unused by the system application. The method has been validated resorting to both an architectural and a memory fault simulator.
      PubDate: 2014-06-15
  • A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and
    • Abstract: Abstract This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS’85 and ITC’99 benchmark circuits show that our approach has an area cost of about 3 % to 6 % with a power consumption saving of about 33 % compared to TMR architectures.
      PubDate: 2014-06-08
  • Editorial
    • PubDate: 2014-06-01
  • Test Technology Newsletter
    • PubDate: 2014-06-01
  • Research on the Efficiency Improvement of Design for Testability Using
           Test Point Allocation
    • Abstract: Abstract Traditional design for testability (DFT) is arduous and time-consuming because of the iterative process of testability assessment and design modification. To improve the DFT efficiency, a DFT process based on test point allocation is proposed. In this process, the set of optimal test points will be automatically allocated according to the signal reachability under the constraints of testability criteria. Thus, the iterative DFT process will be completed by computer and the test engineers will be released to concentrate on the system design rather than the repetitive modification process. To perform test point allocation, the dependency matrix of signal to potential test point (SP-matrix) is defined based on multi-signal flow graph. Then, genetic algorithm (GA) is adopted to search for the optimal test point allocation solution based on the SP-matrix. At last, experiment is carried out to evaluate the effectiveness of the algorithm.
      PubDate: 2014-05-20
  • The Effect of Temperature-Induced Quiescent Operating Point Shift on
           Single-Event Transient Sensitivity in Analog/Mixed-Signal Circuits
    • Abstract: Abstract This paper discusses the different sensitivities of laser-induced single-event transients (SET) with changed temperature (from 300 to 348 K) for an analog/mixed-signal DC/DC PWM controller IC. Basic analog circuits, such as the amplifier, the comparator, and the current mirror, are selected to perform the experiment. The SET energies for some devices decrease while those for others remain constant. The spice simulation implies that the temperature-induced quiescent operating point shift can dramatically affect the SET sensitivity, especially in a complex analog/mixed-signal system. This effect also gives insights on radiation hardened design and testing in analog/mixed-signal circuits.
      PubDate: 2014-05-15
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