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  Subjects -> ENGINEERING (Total: 2018 journals)
    - CHEMICAL ENGINEERING (161 journals)
    - CIVIL ENGINEERING (154 journals)
    - ELECTRICAL ENGINEERING (86 journals)
    - ENGINEERING (1135 journals)
    - ENGINEERING MECHANICS AND MATERIALS (307 journals)
    - HYDRAULIC ENGINEERING (48 journals)
    - INDUSTRIAL ENGINEERING (52 journals)
    - MECHANICAL ENGINEERING (75 journals)

ENGINEERING (1135 journals)            First | 2 3 4 5 6 7 8 9 | Last

International Journal of Intelligent Systems and Applications in Engineering     Open Access   (Followers: 1)
International Journal of Lifecycle Performance Engineering     Hybrid Journal  
International Journal of Machine Tools and Manufacture     Hybrid Journal   (Followers: 4)
International Journal of Manufacturing Research     Hybrid Journal   (Followers: 5)
International Journal of Manufacturing Technology and Management     Hybrid Journal   (Followers: 7)
International Journal of Materials and Product Technology     Hybrid Journal   (Followers: 4)
International Journal of Mathematical Education in Science and Technology     Hybrid Journal   (Followers: 7)
International Journal of Mathematics in Operational Research     Hybrid Journal   (Followers: 1)
International Journal of Medical Engineering and Informatics     Hybrid Journal   (Followers: 5)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 4)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 1)
International Journal of Microwave Science and Technology     Open Access   (Followers: 2)
International Journal of Mobile Network Design and Innovation     Hybrid Journal   (Followers: 3)
International Journal of Multiphase Flow     Hybrid Journal   (Followers: 2)
International Journal of Nanomanufacturing     Hybrid Journal   (Followers: 1)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Nanotechnology     Hybrid Journal   (Followers: 5)
International Journal of Nanotechnology and Molecular Computation     Full-text available via subscription   (Followers: 3)
International Journal of Navigation and Observation     Open Access   (Followers: 6)
International Journal of Network Management     Hybrid Journal  
International Journal of Nonlinear Sciences and Numerical Simulation     Full-text available via subscription  
International Journal of Numerical Methods for Heat & Fluid Flow     Hybrid Journal   (Followers: 7)
International Journal of Optics     Open Access   (Followers: 1)
International Journal of Organisational Design and Engineering     Hybrid Journal   (Followers: 9)
International Journal of Pattern Recognition and Artificial Intelligence     Hybrid Journal   (Followers: 6)
International Journal of Pavement Engineering     Hybrid Journal   (Followers: 2)
International Journal of Physical Modelling in Geotechnics     Hybrid Journal   (Followers: 3)
International Journal of Plasticity     Hybrid Journal   (Followers: 6)
International Journal of Plastics Technology     Hybrid Journal  
International Journal of Polymer Analysis and Characterization     Hybrid Journal   (Followers: 4)
International Journal of Polymer Science     Open Access   (Followers: 16)
International Journal of Precision Engineering and Manufacturing     Hybrid Journal   (Followers: 5)
International Journal of Precision Technology     Hybrid Journal  
International Journal of Pressure Vessels and Piping     Hybrid Journal   (Followers: 3)
International Journal of Production Economics     Hybrid Journal   (Followers: 13)
International Journal of Quality and Innovation     Hybrid Journal   (Followers: 4)
International Journal of Quality Assurance in Engineering and Technology Education     Full-text available via subscription   (Followers: 2)
International Journal of Quality Engineering and Technology     Hybrid Journal   (Followers: 2)
International Journal of Quantum Information     Hybrid Journal  
International Journal of Rapid Manufacturing     Hybrid Journal   (Followers: 1)
International Journal of Reliability, Quality and Safety Engineering     Hybrid Journal   (Followers: 6)
International Journal of Renewable Energy Technology     Hybrid Journal   (Followers: 8)
International Journal of Robust and Nonlinear Control     Hybrid Journal   (Followers: 2)
International Journal of Science Engineering and Advance Technology     Open Access  
International Journal of Sediment Research     Full-text available via subscription   (Followers: 1)
International Journal of Self-Propagating High-Temperature Synthesis     Hybrid Journal   (Followers: 2)
International Journal of Signal and Imaging Systems Engineering     Hybrid Journal  
International Journal of Six Sigma and Competitive Advantage     Hybrid Journal  
International Journal of Social Robotics     Hybrid Journal   (Followers: 1)
International Journal of Software Engineering and Knowledge Engineering     Hybrid Journal   (Followers: 1)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 2)
International Journal of Speech Technology     Hybrid Journal   (Followers: 3)
International Journal of Spray and Combustion Dynamics     Full-text available via subscription   (Followers: 6)
International Journal of Surface Engineering and Interdisciplinary Materials Science     Full-text available via subscription   (Followers: 1)
International Journal of Surface Science and Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Manufacturing     Hybrid Journal   (Followers: 4)
International Journal of Systems and Service-Oriented Engineering     Full-text available via subscription  
International Journal of Systems Assurance Engineering and Management     Hybrid Journal  
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 2)
International Journal of Technoethics     Full-text available via subscription  
International Journal of Technology Management and Sustainable Development     Hybrid Journal   (Followers: 1)
International Journal of Technology Policy and Law     Hybrid Journal   (Followers: 4)
International Journal of Telemedicine and Applications     Open Access   (Followers: 2)
International Journal of Thermal Sciences     Hybrid Journal   (Followers: 5)
International Journal of Thermodynamics     Open Access   (Followers: 2)
International Journal of Turbo & Jet-Engines     Full-text available via subscription  
International Journal of Ultra Wideband Communications and Systems     Hybrid Journal  
International Journal of Vehicle Autonomous Systems     Hybrid Journal   (Followers: 1)
International Journal of Vehicle Design     Hybrid Journal   (Followers: 6)
International Journal of Vehicle Information and Communication Systems     Hybrid Journal   (Followers: 2)
International Journal of Vehicle Noise and Vibration     Hybrid Journal   (Followers: 3)
International Journal of Vehicle Safety     Hybrid Journal   (Followers: 5)
International Journal of Vehicular Technology     Open Access   (Followers: 2)
International Journal of Virtual Technology and Multimedia     Hybrid Journal   (Followers: 4)
International Journal of Wavelets, Multiresolution and Information Processing     Hybrid Journal  
International Journal on Artificial Intelligence Tools     Hybrid Journal   (Followers: 4)
International Nano Letters     Open Access   (Followers: 9)
International Review of Applied Sciences and Engineering     Full-text available via subscription  
Inverse Problems in Science and Engineering     Hybrid Journal   (Followers: 2)
Ionics     Hybrid Journal  
IPTEK The Journal for Technology and Science     Open Access  
IRBM News     Full-text available via subscription  
Irrigation and Drainage Systems     Hybrid Journal  
ISA Transactions     Full-text available via subscription   (Followers: 1)
ISRN - International Scholarly Research Notices     Open Access   (Followers: 68)
ISRN Nanotechnology     Open Access  
ISRN Signal Processing     Open Access  
ISRN Thermodynamics     Open Access  
IT Professional     Full-text available via subscription   (Followers: 3)
Journal of Biosensors & Bioelectronics     Open Access   (Followers: 2)
Journal of Advanced Manufacturing Systems     Hybrid Journal   (Followers: 6)
Journal of Aerosol Science     Hybrid Journal   (Followers: 1)
Journal of Aerospace Engineering     Full-text available via subscription   (Followers: 169)
Journal of Alloys and Compounds     Hybrid Journal   (Followers: 8)
Journal of Analytical and Applied Pyrolysis     Hybrid Journal   (Followers: 3)
Journal of Analytical Science & Technology     Open Access   (Followers: 4)
Journal of Analytical Sciences, Methods and Instrumentation     Open Access   (Followers: 1)
Journal of Applied Analysis     Full-text available via subscription  
Journal of Applied and Industrial Sciences     Open Access  

  First | 2 3 4 5 6 7 8 9 | Last

Journal Cover Journal of Electronic Testing
   [3 followers]  Follow    
   Hybrid Journal Hybrid journal (It can contain Open Access articles)
     ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
     Published by Springer-Verlag Homepage  [2210 journals]   [SJR: 0.424]   [H-I: 22]
  • Pattern Generation for Understanding Timing Sensitivity to Power Supply
           Noise
    • Abstract: Abstract Timing prediction has become more and more difficult with shrinking technology nodes. Combining the pre-silicon delay model with post-silicon timing measurements has the potential to improve the accuracy of timing analysis. In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Long paths are selected from a pseudo functional test set to span the power delivery network. To determine the sensitivity of timing to on-chip noise, the patterns are intelligently filled to achieve the desired PSN level. Our previous PSN control scheme is enhanced to consider both spatial and temporal information for better correlation with functional PSN. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high.
      PubDate: 2014-12-20
       
  • Compressive Sampling Coupled OFDM Technique for Testing Continuous Wave
           Radar
    • Abstract: Abstract Testing continuous wave (CW) radar circuitry is a challenging and time consuming process that requires characterizing system response over a wide range of frequencies. Step frequency continuous wave (SFCW) functional test is widely adopted for CW radar through a large number of frequency tones generation and characterization. For an ultra-wideband radar system, SFCW testing can be very time consuming. In this paper, we propose a new approach to increase test speed at low cost and low design overhead by combining OFDM (Orthogonal Frequency Division Multiplexing) in conjunction with compressive sampling (CS) algorithm. In the test, OFDM is applied for multi-tone signal generation while compressive sampling is for frequency tone reduction. To show equivalent test performance, SFCW test and OFDM-CS test are both performed to characterize a sample ground penetrating radar (GPR). Simulation results are presented for validations.
      PubDate: 2014-12-19
       
  • Pseudo Functional Path Delay Test through Embedded Memories
    • Abstract: Abstract Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these methods do not focus on the interaction between memory and surrounding logic, so may not cover timing critical paths. In this paper, we propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate (PKLPG). Long paths captured into a non-scan cell (including a memory cell) are propagated to a scan cell or primary output, and non-scan cells are initialized so that they can launch transitions onto long paths. This allows scan tests to cover critical paths into and out of memory arrays.
      PubDate: 2014-12-18
       
  • Efficient LFSR Reseeding Based on Internal-Response Feedback
    • Abstract: Abstract LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten test-application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a net-selection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 –2.75 % of internal nets and with 2.35 –4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.
      PubDate: 2014-12-01
       
  • 2013 JETTA-TTTC Best Paper Award
    • PubDate: 2014-11-29
       
  • Low-Cost Concurrent Error Detection for GCM and CCM
    • Abstract: Abstract In many applications, encryption alone does not provide enough security. To enhance security, dedicated authenticated encryption (AE) mode are invented. Galios Counter Mode (GCM) and Counter with CBC-MAC mode (CCM) are the AE modes recommended by the National Institute of Standards and Technology. To support high data rates, AE modes are usually implemented in hardware. However, natural faults reduce its reliability and may undermine both its encryption and authentication capability. We present a low-cost concurrent error detection (CED) scheme for 7 AE architectures. The proposed technique explores idle cycles of the AE mode architectures. Experimental results shows that the performance overhead can be lower than 100 % for all architectures depending on the workload. FPGA implementation results show that the hardware overhead in the 0.1–23.3 % range and the power overhead is in the 0.2–23.2 % range. ASIC implementation results show that the hardware overhead in the 0.1–22.8 % range and the power overhead is in the 0.3–12.6 % range. The underlying block cipher and hash module need not have CED built in. Thus, it allows system designers to integrate block cipher and hash function intellectual property from different vendors.
      PubDate: 2014-11-29
       
  • Editorial
    • PubDate: 2014-11-28
       
  • On-Wafer Calibration Technique for High Frequency Measurement with
           Simultaneous Voltage and Current Tuning
    • Abstract: Abstract This paper presents a novel on wafer calibration method for the measurement of radio RF passive components with R&S vector network analyzer (VNA) at RF and mm-wave frequency. This method has employed the high frequency structure simulator (HFSS) results along with multi-level optimizations to get the nominal values used for on wafer calibration. Multiline (Thru-reflect-line) TRL calibration standards fabricated on the same substrate are used with better accuracy. Measured results show that a thru line provides less than 0.015 dB insertion loss throughout the frequency range of 1GHz-67GHz. This result is much better compared to the results achieved by conventional Short-open-load-thru (SOLT) calibration and (Thru-reflect-line) TRL calibration using the available calibration substrates. Using this calibration technique, the phase variation of the thru line shows less than 3° at 67GHz which is much lower than 15° achieved by the conventional calibration methods. The measurement of the multi band characteristics of the RF passive components by simultaneous current and voltage application has also been demonstrated successfully.
      PubDate: 2014-11-28
       
  • Single Event Resilient Dynamic Logic Designs
    • Abstract: Abstract Dynamic logic families are commonly used in high speed applications, but they are susceptible to single event errors. This paper presents and evaluates three techniques of hardening dynamic logic—layout manipulation using charge sharing, addition of a feedback capacitor across the static inverter, and dual-rail domino logic with differential keepers. The layout-based design has better single event tolerance by sharing charge between NFET devices of the dynamic and static inverters; the design with a feedback capacitor makes the keeper more effective in recovering the hit node because of the increased propagation delay; the differential-keeper structure shows superior SET performance because the hit node could recover through the restoring path in the case of charge loss. These proposed designs along with the reference traditional keeper-based design were fabricated in a 130 nm technology node as shift register chains and then irradiated by heavy ion particles. Experimental results verified the mechanisms and effectiveness of these proposed designs.
      PubDate: 2014-11-27
       
  • Improving Semiconductor Reliability with Advanced Engineering Methods in
           Test Program Development
    • Abstract: Abstract Advancing semiconductor technology in combination with new assembly and packaging technologies are unfolding a new level of challenges for production testing. Reliability of semiconductors should be ensured by applying dedicated techniques within production testing addressing various aging aspects such as: device wear-out related degradation or reduced operational voltage headroom. Thus, test program quality is emerging as a major concern, as it is directly translating into microelectronics reliability and devices quality. With the heightened sensitivity of semiconductor technology to smallest deviations in test methods from the allowed operational range, the risk of accidentally degrading the integrated circuits reliability increases significant. In this paper we propose an approach that addresses the demand for improving semiconductor technology reliability production tests quality. The presented industry usage based case studies, in combination with described techniques, provide a set of valuable practical guidelines.
      PubDate: 2014-11-19
       
  • Test Technology Newsletter
    • PubDate: 2014-11-14
       
  • On-line Condition Monitoring and Maintenance of Power Electronic
           Converters
    • Abstract: Abstract This paper presents on-line technique for condition based maintenance of power electronic converters. The wear-out condition for high failure rate components is obtained based on parametric degradation. As per MIL Handbook 217 F, electrolytic capacitors and switching transistors together constitutes more than 90 % failures of power electronic systems. An electronic control gear circuit for fluorescent lamp is designed for on-line condition monitoring of target aluminum electrolytic capacitors and MOSFET at an accelerated aging condition. A low cost microcontroller board is programmed for data acquisition and test circuit control. Data values are serially communicated to National Instruments LabVIEW software, installed on the host computer for algorithm implementation and condition based maintenance of circuit. Using web publishing tool, the control of running state front panel VI is continuously transferred from local host to the client as an HTML file that is accessed in standard web browsers. Operator can remotely monitor the health of life limiting devices and can perform condition based shut down of the circuit. Also parametric data values of target devices are stored on hard disk of host computer in MS Excel file.
      PubDate: 2014-11-09
       
  • Efficient Error-Tolerability Testing on Image Processing Circuits Based on
           Equivalent Error Rate Transformation
    • Abstract: Abstract In this paper we address two key issues related to error-tolerability testing on image processing circuits, namely acceptable threshold determination and acceptability evaluation. A JPEG 2000 decoder is employed as a case study. We first carefully investigate the acceptability threshold values of images in terms of error rate and error significance. The investigation results show that appropriate threshold values should be determined depending on a number of factors, including size (resolution), brightness, contrast and frequency of test images as well as human subjectiveness. Based on the determined threshold values we propose an equivalent error rate transformation technique to help test engineers easily and quickly examine the acceptability of a circuit under test. We also carry out hardware implementation of the proposed technique. The implementation results show that the hardware area overhead with respect to a commercial JPEG decoder design is only 2.24 %. To validate the proposed technique, 13,860 erroneous color images produced by faulty JPEG 2000 decoders as well as 450 erroneous benchmark images are employed. The experimental results show that the proposed technique is as effective as the exhaustive test method. Moreover, our technique requires much less test time and storage space compared with the exhaustive test method. The achievable reduction ratio in test time and storage space is more than 99 %.
      PubDate: 2014-11-05
       
  • A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator
    • Abstract: Abstract This paper proposes a small chip area stochastic calibration for TDC linearity and input range, and analyzes it with FPGA. The proposed calibration estimates the absolute values of the delay of the buffers and the range of measurement statistically. The hardware implementation of the proposed calibration requires single counter to construct the histogram, so that the extra area for the proposed calibration is smaller. Because the implementation is fully digital, it is easily implemented on digital LSIs such as FPGA, micro-processor, and SoC. Experiments with Xilinx Virtex-5 LX FPGA ML501 reveal that both the periods of the external clock and the ring oscillator are preferred as short as possible under more than twice of the range of measurement of TDC when the oscillation period of the ring oscillator is wider than that of the external clock for fast convergence. The required time for the proposed calibration is 0.08 ms, and the required hardware resources LUTs and FFs for the implementation on FPGA are 24.1% and 22.2% of the conventional implementation, respectively.
      PubDate: 2014-11-05
       
  • Testing Disturbance Faults in Various NAND Flash Memories
    • Abstract: Abstract NAND flash memory is one popular non-volatile memory. Flash memory is prone to disturbance faults due to its specific mechanism of functional operations. Furthermore, different NAND flash memories might be different on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot; some NAND flash memories with single-page wordlines and some with multiple-page wordlines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are proposed.
      PubDate: 2014-11-01
       
  • Diagnostic Test Generation for Transition Delay Faults Using Stuck-At
           Fault Detection Tools
    • Abstract: Abstract By adding a few logic gates and one or two modeling flip-flops to the circuit under test (CUT), we create a detection or diagnostic automatic test pattern generation (ATPG) model of transition delay faults usable by a conventional single stuck-at fault test pattern generator. Given a transition delay fault pair, the diagnostic ATPG model can either find an exclusive test or prove the equivalence of the fault pair. Our work offers advantages over existing work. First, the detection of a transition delay fault or the diagnosis of a fault pair can be modeled in only one instead of two or four time-frames of the CUT. Second, an exclusive test can be generated under either launch off capture (LOC) or launch off shift (LOS) mode for a full-scan sequential circuit. Third, the proposed ATPG models can be expanded into two time frames to facilitate the use of combinational ATPG tools, though with lower modeling complexity than was possible before. As a result, the percentage of distinguished transition delay fault pairs is larger and the proposed automatic exclusive test generation system is more time-efficient.
      PubDate: 2014-10-31
       
  • Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR
           Based Emulators
    • Abstract: Abstract Evaluation of the single event upsets (SEUs) impact on SRAM-based FPGAs is a major issue in the adoption of these FPGAs in aerospace applications. In this context, different approaches have been recorded in the literatures, among which the emulation methods are applied most frequently regarding their proper cost-effectiveness and time-saving aspects. This paper has proposed a new approach for increasing the SEU emulation rate in the dynamic partial reconfiguration (DPR)-based emulators. Unlike the traditional procedure that emulates the SEU faults only in one loop, the proposed three-level management algorithm (3-LMA) consists of three nested loops. Theoretical analysis and experimental results show that the suggested technique is to some orders of magnitude faster than traditional approach.
      PubDate: 2014-10-28
       
  • Characterization of a Passive Telemetric System for ISM Band Pressure
           Sensors
    • Abstract: Abstract This paper presents a passive telemetric system for ISM band pressure sensors. The passive telemetric system is consisted of an external planar spiral coil and a pressure sensor. Theoretical analysis for the principle of the telemetric technique is described. Since the sensitivity and efficiency of the telemetric system is related with the performance of the pressure sensor and external coil. The characterization of the critical parameters for the design of pressure sensor and inductive coils are presented and analyzed separately. The characteristic impedance of the system, expressed as the function of the frequency, is measured by R&S ZVA67 VNA. The Measurement results show that the resonant frequency of the pressure sensor can shift from 397.83 to 396.84 MHz with an increasing pressure from 0 to 100 mmHg. This measurement proves the work of the telemetric system and also reflects that the ISM band pressure sensor has a high pressure sensitivity of 0.92 KHz/mmHg.
      PubDate: 2014-10-25
       
  • Access Port Protection for Reconfigurable Scan Networks
    • Abstract: Abstract Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-the-art protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multi-level access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.
      PubDate: 2014-10-18
       
  • Test Technology Newsletter
    • PubDate: 2014-09-23
       
 
 
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