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  Subjects -> ENGINEERING (Total: 2156 journals)
    - CHEMICAL ENGINEERING (186 journals)
    - CIVIL ENGINEERING (168 journals)
    - ELECTRICAL ENGINEERING (93 journals)
    - ENGINEERING (1164 journals)
    - ENGINEERING MECHANICS AND MATERIALS (355 journals)
    - HYDRAULIC ENGINEERING (55 journals)
    - INDUSTRIAL ENGINEERING (54 journals)
    - MECHANICAL ENGINEERING (81 journals)

ENGINEERING (1164 journals)            First | 2 3 4 5 6 7 8 9 | Last

International Journal of Hypersonics     Full-text available via subscription   (Followers: 3)
International Journal of Imaging Systems and Technology     Hybrid Journal   (Followers: 2)
International Journal of Impact Engineering     Hybrid Journal   (Followers: 8)
International Journal of Information Acquisition     Hybrid Journal   (Followers: 1)
International Journal of Innovation and Applied Studies     Open Access   (Followers: 3)
International Journal of Innovation Science     Full-text available via subscription   (Followers: 6)
International Journal of Innovative Technology and Research     Open Access  
International Journal of Integrated Engineering     Open Access   (Followers: 1)
International Journal of Intelligent Engineering Informatics     Hybrid Journal  
International Journal of Intelligent Systems and Applications in Engineering     Open Access  
International Journal of Lifecycle Performance Engineering     Hybrid Journal   (Followers: 1)
International Journal of Machine Tools and Manufacture     Hybrid Journal   (Followers: 5)
International Journal of Manufacturing Research     Hybrid Journal   (Followers: 5)
International Journal of Manufacturing Technology and Management     Hybrid Journal   (Followers: 7)
International Journal of Materials and Product Technology     Hybrid Journal   (Followers: 4)
International Journal of Mathematical Education in Science and Technology     Hybrid Journal   (Followers: 8)
International Journal of Mathematics in Operational Research     Hybrid Journal   (Followers: 1)
International Journal of Medical Engineering and Informatics     Hybrid Journal   (Followers: 5)
International Journal of Micro Air Vehicles     Full-text available via subscription   (Followers: 4)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (Followers: 1)
International Journal of Microwave Science and Technology     Open Access   (Followers: 2)
International Journal of Mobile Network Design and Innovation     Hybrid Journal   (Followers: 3)
International Journal of Multiphase Flow     Hybrid Journal   (Followers: 2)
International Journal of Nanomanufacturing     Hybrid Journal   (Followers: 1)
International Journal of Nanoscience     Hybrid Journal   (Followers: 1)
International Journal of Nanotechnology     Hybrid Journal   (Followers: 5)
International Journal of Nanotechnology and Molecular Computation     Full-text available via subscription   (Followers: 3)
International Journal of Navigation and Observation     Open Access   (Followers: 11)
International Journal of Network Management     Hybrid Journal  
International Journal of Nonlinear Sciences and Numerical Simulation     Hybrid Journal  
International Journal of Numerical Methods for Heat & Fluid Flow     Hybrid Journal   (Followers: 7)
International Journal of Optics     Open Access   (Followers: 1)
International Journal of Organisational Design and Engineering     Hybrid Journal   (Followers: 10)
International Journal of Pattern Recognition and Artificial Intelligence     Hybrid Journal   (Followers: 6)
International Journal of Pavement Engineering     Hybrid Journal   (Followers: 3)
International Journal of Physical Modelling in Geotechnics     Hybrid Journal   (Followers: 3)
International Journal of Plasticity     Hybrid Journal   (Followers: 6)
International Journal of Plastics Technology     Hybrid Journal   (Followers: 1)
International Journal of Polymer Analysis and Characterization     Hybrid Journal   (Followers: 5)
International Journal of Polymer Science     Open Access   (Followers: 20)
International Journal of Precision Engineering and Manufacturing     Hybrid Journal   (Followers: 5)
International Journal of Precision Engineering and Manufacturing-Green Technology     Hybrid Journal  
International Journal of Precision Technology     Hybrid Journal  
International Journal of Pressure Vessels and Piping     Hybrid Journal   (Followers: 3)
International Journal of Production Economics     Hybrid Journal   (Followers: 13)
International Journal of Quality and Innovation     Hybrid Journal   (Followers: 4)
International Journal of Quality Assurance in Engineering and Technology Education     Full-text available via subscription   (Followers: 2)
International Journal of Quality Engineering and Technology     Hybrid Journal   (Followers: 2)
International Journal of Quantum Information     Hybrid Journal  
International Journal of Rapid Manufacturing     Hybrid Journal   (Followers: 3)
International Journal of Reliability, Quality and Safety Engineering     Hybrid Journal   (Followers: 7)
International Journal of Renewable Energy Technology     Hybrid Journal   (Followers: 9)
International Journal of Robust and Nonlinear Control     Hybrid Journal   (Followers: 3)
International Journal of Science Engineering and Advance Technology     Open Access  
International Journal of Sediment Research     Full-text available via subscription   (Followers: 1)
International Journal of Self-Propagating High-Temperature Synthesis     Hybrid Journal   (Followers: 2)
International Journal of Signal and Imaging Systems Engineering     Hybrid Journal  
International Journal of Six Sigma and Competitive Advantage     Hybrid Journal  
International Journal of Social Robotics     Hybrid Journal   (Followers: 2)
International Journal of Software Engineering and Knowledge Engineering     Hybrid Journal   (Followers: 2)
International Journal of Space Science and Engineering     Hybrid Journal   (Followers: 2)
International Journal of Speech Technology     Hybrid Journal   (Followers: 4)
International Journal of Spray and Combustion Dynamics     Full-text available via subscription   (Followers: 6)
International Journal of Superconductivity     Open Access  
International Journal of Surface Engineering and Interdisciplinary Materials Science     Full-text available via subscription   (Followers: 1)
International Journal of Surface Science and Engineering     Hybrid Journal   (Followers: 8)
International Journal of Sustainable Engineering     Hybrid Journal   (Followers: 7)
International Journal of Sustainable Manufacturing     Hybrid Journal   (Followers: 4)
International Journal of Systems and Service-Oriented Engineering     Full-text available via subscription  
International Journal of Systems Assurance Engineering and Management     Hybrid Journal  
International Journal of Systems, Control and Communications     Hybrid Journal   (Followers: 2)
International Journal of Technoethics     Full-text available via subscription   (Followers: 1)
International Journal of Technology Management and Sustainable Development     Hybrid Journal   (Followers: 1)
International Journal of Technology Policy and Law     Hybrid Journal   (Followers: 5)
International Journal of Telemedicine and Applications     Open Access   (Followers: 2)
International Journal of Thermal Sciences     Hybrid Journal   (Followers: 7)
International Journal of Thermodynamics     Open Access   (Followers: 2)
International Journal of Turbo & Jet-Engines     Hybrid Journal  
International Journal of Ultra Wideband Communications and Systems     Hybrid Journal  
International Journal of Vehicle Autonomous Systems     Hybrid Journal   (Followers: 1)
International Journal of Vehicle Design     Hybrid Journal   (Followers: 8)
International Journal of Vehicle Information and Communication Systems     Hybrid Journal   (Followers: 2)
International Journal of Vehicle Noise and Vibration     Hybrid Journal   (Followers: 3)
International Journal of Vehicle Safety     Hybrid Journal   (Followers: 5)
International Journal of Vehicular Technology     Open Access   (Followers: 3)
International Journal of Virtual Technology and Multimedia     Hybrid Journal   (Followers: 4)
International Journal of Wavelets, Multiresolution and Information Processing     Hybrid Journal  
International Journal on Artificial Intelligence Tools     Hybrid Journal   (Followers: 4)
International Nano Letters     Open Access   (Followers: 9)
International Review of Applied Sciences and Engineering     Full-text available via subscription  
International Scholarly Research Notices     Open Access   (Followers: 225)
Inverse Problems in Science and Engineering     Hybrid Journal   (Followers: 2)
Ionics     Hybrid Journal  
IPTEK The Journal for Technology and Science     Open Access  
IRBM News     Full-text available via subscription  
Ironmaking & Steelmaking     Hybrid Journal   (Followers: 2)
Irrigation and Drainage Systems     Hybrid Journal   (Followers: 1)
ISA Transactions     Full-text available via subscription   (Followers: 1)
IT Professional     Full-text available via subscription   (Followers: 3)
Johnson Matthey Technology Review     Open Access   (Followers: 2)

  First | 2 3 4 5 6 7 8 9 | Last

Journal Cover   Journal of Electronic Testing
  [SJR: 0.241]   [H-I: 24]   [1 followers]  Follow
    
   Hybrid Journal Hybrid journal (It can contain Open Access articles)
   ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
   Published by Springer-Verlag Homepage  [2299 journals]
  • Test Technology Newsletter
    • PubDate: 2015-06-27
       
  • Circuit-Level Simulation of the Single Event Transients in an On-Chip
           Single Event Latchup Protection Switch
    • Abstract: Abstract The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250 nm CMOS process, is presented. The SPS cell provides the latchup protection for standard cells on the principle of power domain control. It is based on a sensing/driving PMOS transistor which acts both as a latchup sensor and a driver for the standard cells, and includes additional PMOS and NMOS transistors for controlling the sensing/driving transistor and interfacing to the external control logic. The previous work has confirmed the SPS cell’s functionality in the case of single event latchup, and the experimental investigation has proven that the SPS cell is immune to single event latchup for LET values up to 74.8 MeV∙cm2/mg. This case study extends the previous research by introducing the circuit-level simulation of the SPS cell’s response to the single event transients (SETs). Using the square pulse current as a SET model, the amplitude and duration of the SET-induced voltage pulses at the SPS cell’s outputs have been analyzed with respect to the injected charge, operating temperature, supply voltage, load (number of standard cells connected to the SPS cell) and sensing/driving transistor’s channel width. The results have shown that the immunity of the SPS cell to SETs can be significantly enhanced by connecting a larger number of standard cells to the SPS cell and increasing the sensing/driving transistor’s size, without any area overhead. An analytical expression for calculating the critical charge in terms of the transistor size and the number of standard cells connected to the SPS cell has been derived. Moreover, the SPS cell can be used as a SET sensor for detecting the levels of injected charge which cannot be mitigated by the increase of transistor size and load, and in conjunction with the external control logic it could be possible to measure the SET duration and perform online corrections of the SET-induced faults in the standard cells supplied by the SPS cell.
      PubDate: 2015-06-26
       
  • Editorial
    • PubDate: 2015-06-25
       
  • A New Approach to Model the Effect of Topology on Testing Using Boundary
           Scan
    • Abstract: Abstract In this paper, a new analytical approach is presented to study the effect of commonly used topologies on the energy consumption and delay of on chip network (NOC) testing using IEEE 1149.1 standard. Here, first we model the energy of each module in JTAG standard, and then using test access port (TAP) controller state diagram and test algorithm, the totoal energy based on each topology is calculated. In addition, the number of clocks is calculated and together with the propagation delay of basic gates, the test time is modelled and calculated. Using the results we can choose the least energy-consuming and fastet topology in terms of testing. The modelling is verified using FPGA implementation.
      PubDate: 2015-06-24
       
  • A Unified Sequential Equivalence Checking Methodology to Verify RTL
           Designs with High-Level Functional and Protocol Specification Models
    • Abstract: Abstract Digital application complexity has steadily made it harder to discover and debug behavioral inconsistencies at register transfer level (RTL). Aiming to bring a solution, several techniques have appeared as alternatives to verify that a circuit description meets the requirements of its corresponding functional specification. Simulation-based verification is still far from reaching high state coverage because of cycle-accurate slowness. Formal approaches are exhaustive in theory, but due to computational limitations, workarounds must always be adopted to check only a portion of the design at a time. Bounded model checking is one of the most popular formal methods; however, a strong disadvantage resides in defining and determining the quality of the set of properties to verify. Sequential equivalence checking is also an effective alternative, but it can only be applied between circuit descriptions where a one-to-one correspondence for states and memory elements is expected. This paper presents a formal methodology to verify RTL descriptions through direct comparison with: 1) a high-level reference model and 2) a protocol reference model. Thus, it is possible to verify behavioral and interface protocol separately. Complete sequences of states are extracted from the reference models and the RTL design, and compared to determine if the design implementation is correct. The natural discrepancies between the models and RTL code are considered, including non-matching interface and memory elements, state mapping, and process concurrency. The validity of the methodology is formally justified and a related tool was developed to show, through examples, that the approach may be applied on real designs.
      PubDate: 2015-06-16
       
  • One More Class of Sequential Circuits having Combinational Test Generation
           Complexity
    • Abstract: Abstract The paper uses the concept of time expansion model to find the test generation for acyclic sequential circuits. Any acyclic sequential circuit without hold registers can be tested with combinational test generation complexity using this model. We show that for acyclic sequential circuits having hold registers, a subset of such circuits can also be tested with this complexity. We define the max-testable class of sequential circuits that includes both these groups. The paper also suggests an algorithm to find such class of circuits.
      PubDate: 2015-06-11
       
  • A New On-chip Signal Generator for Charge-Based Capacitance Measurement
           Circuit
    • Abstract: Abstract In this paper, a new on-chip signal generator for charge-based capacitance measurement (CBCM) circuit is proposed. As compared to conventional circuits that use two input off-chip clock signals or on-chip delay cells, the proposed circuit uses an I/Q splitter and an AND function to obtain 1/2 and 1/8 duty cycle signals, hence reduces the potential mismatch between these two clock signals. The proposed circuit makes it possible to use higher input frequency in measurement. As a result, smaller capacitance can be measured using the same measurement facilities without the loss of accuracy. Implemented in a standard 180 nm CMOS process, the proposed signal generator only occupies 40 μm × 18 μm while consuming less than 60 μW at an input frequency of 100 MHz. Simulation and measurement results suggest that the CBCM measuring circuits with proposed signal generator achieves the same accuracy as compared to conventional circuits while the requirement of measurement facilities can be considerably relaxed.
      PubDate: 2015-05-31
       
  • Distributed Scan Like Fault Detection and Test Optimization for Digital
           Microfluidic Biochips
    • Abstract: Abstract Development of digital microfluidic biochips (DMFB) has faced a major setback from the threats of faulty and erroneous fluidic operations. Defective electrodes are the main reason for this misleading assay performance. It also affects the assay completion time and overall turnaround time. In this present article, a fast fault diagnosis mechanism is discussed to identify the defective locations of electrode array. The proposed fault detection method is governed by a distributed dispensing and scheduling of test droplets on a 2-D biochip. Water droplets are strategically routed across the DMFB board and quantified at every location using cost effective photodiode sensors. Multiple test droplets are routed on the chip in a time synchronized manner to avoid any routing conflict or failure in diagnosis. This concurrent test droplet circulation incurs optimum layover period and parallel and multiple test droplet movement enhances the fault detection performance. Completeness of the fault analysis is ensured with a sequential post processing as well. Test results of this approach have recorded some substantial improvement in terms of fault detection time and accuracy.
      PubDate: 2015-05-31
       
  • A Hilbert-Transform-Based Method to Estimate and Correct Timing Error in
           Time-Interleaved ADCs
    • Abstract: Abstract In time-interleaved analog-to-digital converter (ADC) architecture, offset mismatch, gain mismatch, and timing error between channels degrade the performance of time-interleaved ADCs. This paper focuses on the timing error, and proposes a simple calibration algorithm based on Hilbert transform estimate and then correct the timing error. With a cosine input, it could efficiently and accurately estimate the timing error. Fractional delay filters are developed to correct the timing errors. This simplifies the design and decreases the cost. Numerical simulations are used to verify the proposed estimation and correction algorithm.
      PubDate: 2015-04-29
       
  • Formal Quantification of the Register Vulnerabilities to Soft Error in RTL
           Control Paths
    • Abstract: Radiation-induced soft error is a significant reliability issue in nanoscale technology nodes. As the sequential registers are major contributors to the system soft error rate, accurate analysis of their vulnerabilities at early design phases is essential for cost-efficient error mitigation. In this paper, a novel approach is proposed to quantify the soft error vulnerabilities of the registers in control paths at Register-Transfer Level (RTL). By modeling the control path as a state transition system, formal probabilistic model checking is adopted to compute the register vulnerabilities by taking the workload dependency into consideration. Efficient RTL abstraction and model simplification techniques are proposed to achieve an exponential reduction of the state space, enabling our methodology to analyze large control modules in a typical embedded processor. The experimental results show the effectiveness of the proposed techniques, which can successfully quantify the non-uniform register vulnerabilities in RTL designs.
      PubDate: 2015-04-11
       
  • Editorial
    • PubDate: 2015-04-08
       
  • Test Technology Newsletter
    • PubDate: 2015-04-08
       
  • Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion
           Correction
    • Abstract: Abstract Delay line ADCs are becoming increasingly attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we first present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. In order to reduce the convergence time of the calibration, we inject a periodic 3-bit gray code sequence instead of three pseudorandom numbers for harmonic distortion correction to digitally calibrate an 8-bit delay line ADC. In our simulation results, the SNDR is significantly improved from 25.6 dB to 42.5 dB, with a calibration time of 13.5 milliseconds, which is 64X faster than harmonic distortion correction with the pseudorandom numbers.
      PubDate: 2015-04-01
       
  • Analog Circuits Soft Fault Diagnosis Using Rényi’s Entropy
    • Abstract: Abstract An analog circuit soft fault diagnosis method using Rényi’s entropy is proposed. This method focuses on extracting the entropy information contained in the probability density function (PDF) of the output of the circuit under test (CUT), which is sensitive to the parameters of circuits. Firstly, using the Lagrange multiplier method with Rényi’s entropy deduces PDF. Then the parameter α of Rényi’s entropy is estimated adaptively by employing the output of CUT through the maximum likelihood estimation method. Finally, the value of Rényi’s entropy can be calculated using the PDF and α parameter. The divergence between the Rényi’s entropy corresponding to the fault and fault free circuits is adopted to detect the fault. The method can detect soft fautls, including the single fault and multiple faults, without complicated models and mass of data, and also without interrupting the inherent connections. We conduct experiments respectively on two circuits that are implemented on an actual circuit board. The effectiveness of the proposed method is demonstrated by the result of the experiment.
      PubDate: 2015-03-29
       
  • Scalable and Optimized Hybrid Verification of Embedded Software
    • Abstract: Abstract The verification of embedded software has become an important subject over the last years. However, neither standalone verification approaches, like simulation-based/formal verification, nor state-of-the-art semiformal verification approaches are able to verify large and complex embedded software with or without hardware dependencies. This work presents a scalable hybrid verification approach for the verification of embedded software using a semiformal algorithm optimized with static parameter assignment (SPA). These algorithms and methodologies like SPA and counterexample guided simulation are used to combine simulation-based and formal verification in a new way. SPA offers a method to interact between dynamic and static verification approaches based on an automated ranking determination of possible function parameters according to the impact on the model size. Furthermore, SPA inserts initialization code for specific function parameters into the source code under test and supports model building and optimization algorithms to reduce the state space. We have successfully applied this optimized hybrid verification methodology to embedded software applications: Motorola’s Powerstone Benchmark suite and a complex automotive industrial embedded software. The results show that our approach scales better than standalone software model checkers to reach deep state spaces.
      PubDate: 2015-03-27
       
  • A Determinate Radiation Hardened Technique for Safety-Critical CMOS
           Designs
    • Abstract: Abstract Soft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical designs. Triple modular redundancy (TMR) is widely used to mask virtually all soft errors but typically incurs high power and area overheads. Therefore, in this paper, a determinate radiation hardened technique for safety-critical CMOS designs is proposed and consists of three hybrid strategies combining gate sizing, supply voltage (V D D ) scaling and threshold voltage (V t h ) scaling to prevent soft errors from occurring. A STA-like method that computes the required pulse width of a transient fault along the propagation path is also developed in this framework. Simulation results show that the proposed technique can effectively eliminate all soft errors on ISCAS’85 circuits and a controller area network bus electrical control unit (CAN-bus ECU) design for automotive electronics when the deposited charges range from 35 fC to 132 fC. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3.3X and 2X, respectively, compared with TMR.
      PubDate: 2015-03-27
       
  • Reusing RTL Assertion Checkers for Verification of SystemC TLM Models
    • Abstract: The recent trend towards system-level design gives rise to new challenges for reusing existing (RTL) intellectual properties (IPs) and their verification environment in (TLM). While techniques and tools to abstract (RTL) IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still under-explored, particularly when (ABV) is adopted. Some frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet, except by using transactors to create a mixed simulation between the TLM design and the RTL checkers corresponding to the assertions. However, the use of transactors may lead to longer verification time due to the need of developing and verifying the transactors themselves. Moreover, the simulation time is negatively affected by the presence of transactors, which slow down the simulation at the speed of the slowest parts (i.e., RTL checkers). This article proposes an alternative methodology that does not require transactors for reusing assertions, originally defined for a given RTL IP, in order to verify the corresponding TLM model. Experimental results have been conducted on benchmarks with different characteristics and complexity to show the applicability and the efficiency of the proposed methodology.
      PubDate: 2015-03-20
       
  • A Shift-Register Based BIST Architecture for FPGA Global Interconnect
           Testing and Diagnosis
    • Abstract: Abstract This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results.
      PubDate: 2015-03-13
       
  • Application-Based Analysis of Register File Criticality for Reliability
           Assessment in Embedded Microprocessors
    • Abstract: Abstract There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened). This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy compared to previous approaches and regardless of the underlying architecture.
      PubDate: 2015-02-20
       
  • 2014 JETTA Reviewers
    • PubDate: 2015-02-01
       
 
 
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