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  Subjects -> ENGINEERING (Total: 2266 journals)
    - CHEMICAL ENGINEERING (190 journals)
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    - ENGINEERING (1195 journals)
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    - MECHANICAL ENGINEERING (89 journals)

ENGINEERING (1195 journals)            First | 1 2 3 4 5 6 | Last

Showing 1001 - 1200 of 1205 Journals sorted alphabetically
Progress in Nanotechnology and Nanomaterials     Open Access   (Followers: 4)
Progress in Photovoltaics: Research & Applications     Hybrid Journal   (Followers: 6)
Progress in Polymer Science     Full-text available via subscription   (Followers: 32)
Propellants, Explosives, Pyrotechnics     Hybrid Journal   (Followers: 281)
Propulsion and Power Research     Open Access   (Followers: 24)
Purinergic Signalling     Hybrid Journal   (Followers: 1)
Quaderns d’Història de l’Enginyeria     Open Access  
Quality and Reliability Engineering International     Hybrid Journal   (Followers: 14)
Quality Engineering     Hybrid Journal   (Followers: 9)
Radiochimica Acta     Hybrid Journal   (Followers: 5)
Rapid Prototyping Journal     Hybrid Journal   (Followers: 3)
Rare Metals     Hybrid Journal  
Reactive and Functional Polymers     Hybrid Journal   (Followers: 5)
Recent Patents on Engineering     Full-text available via subscription   (Followers: 3)
Recent Patents on Nanotechnology     Full-text available via subscription   (Followers: 3)
Recherche Transports Sécurité     Hybrid Journal   (Followers: 1)
Redes de Ingeniería     Open Access  
Regional Maritime University Journal     Full-text available via subscription   (Followers: 2)
Regular and Chaotic Dynamics     Hybrid Journal  
Rem : Revista Escola de Minas     Open Access   (Followers: 1)
Remote Sensing     Open Access   (Followers: 38)
Remote Sensing Letters     Hybrid Journal   (Followers: 36)
Requirements Engineering     Hybrid Journal   (Followers: 3)
Research Ideas and Outcomes     Open Access  
Research in Engineering Design     Hybrid Journal   (Followers: 11)
Research Journal of Nanoscience and Nanotechnology     Open Access   (Followers: 20)
Research Works of Air Force Institute of Technology     Open Access   (Followers: 1)
Resonance     Hybrid Journal   (Followers: 28)
Reviews in Advanced Sciences and Engineering     Partially Free   (Followers: 2)
Revista AIDIS de Ingeniería y Ciencias Ambientales. Investigación, desarrollo y práctica     Open Access  
Revista Brasileira de Engenharia Agrícola e Ambiental     Open Access   (Followers: 1)
Revista Ciencias e Ingeniería al Día     Open Access  
Revista CINTEX     Open Access   (Followers: 1)
Revista de Engenharia da Universidade Católica de Petrópolis     Open Access  
Revista de Ingeniería     Open Access  
Revista de Ingenieria Sismica     Open Access  
Revista de Investigación, Desarrollo e Innovación     Open Access  
Revista EIA     Open Access   (Followers: 1)
Revista Facultad de Ingeniería     Open Access   (Followers: 1)
Revista Facultad de Ingenieria - Universidad de Tarapaca     Open Access  
Revista Facultad de Ingeniería Universidad de Antioquia     Open Access   (Followers: 1)
Revista Fatec Zona Sul : REFAS     Open Access  
Revista Iberoamericana de Automática e Informática Industrial RIAI     Open Access  
Revista Informador Técnico     Open Access   (Followers: 1)
Revista Ingenieria de Construcción     Open Access  
Revista Internacional de Métodos Numéricos para Cálculo y Diseño en Ingeniería     Open Access  
Revista Logos Ciencia & Tecnología     Open Access  
Revue de Métallurgie     Full-text available via subscription  
Russian Engineering Research     Hybrid Journal  
Russian Journal of Non-Ferrous Metals     Hybrid Journal   (Followers: 22)
Russian Microelectronics     Hybrid Journal   (Followers: 1)
Sadhana     Open Access   (Followers: 7)
Safety Science     Hybrid Journal   (Followers: 29)
Scholedge International Journal of Multidisciplinary & Allied Studies     Open Access   (Followers: 3)
Science & Technique     Open Access  
Science and Education : Scientific Publication of BMSTU     Open Access  
Science and Engineering Ethics     Hybrid Journal   (Followers: 9)
Science and Technology     Open Access   (Followers: 2)
Science China Technological Sciences     Hybrid Journal  
Science Journal of Volgograd State University. Technology and innovations     Open Access  
Science Progress     Full-text available via subscription   (Followers: 3)
Scientia cum Industria     Open Access  
Scientific Drilling     Open Access  
Scientific Journal of Control Engineering     Open Access   (Followers: 1)
Sealing Technology     Full-text available via subscription   (Followers: 1)
Securitas Vialis     Hybrid Journal  
Security and Communication Networks     Hybrid Journal   (Followers: 3)
Selcuk University Journal of Engineering, Science and Technology     Open Access  
Selected Topics in Applied Earth Observations and Remote Sensing, IEEE Journal of     Hybrid Journal   (Followers: 48)
Semiconductors     Hybrid Journal  
Semiconductors and Semimetals     Full-text available via subscription   (Followers: 1)
Sensing and Imaging : An International Journal     Hybrid Journal   (Followers: 2)
Sensor Letters     Full-text available via subscription   (Followers: 2)
Sensors     Open Access   (Followers: 14)
Separation and Purification Technology     Hybrid Journal   (Followers: 9)
Services Computing, IEEE Transactions on     Hybrid Journal   (Followers: 5)
Shock and Vibration     Hybrid Journal   (Followers: 9)
SIAM Journal on Applied Dynamical Systems     Hybrid Journal   (Followers: 2)
SIAM Journal on Mathematical Analysis     Hybrid Journal   (Followers: 3)
SIAM Journal on Matrix Analysis and Applications     Hybrid Journal   (Followers: 1)
SIAM Journal on Numerical Analysis     Hybrid Journal   (Followers: 4)
SIAM Journal on Optimization     Hybrid Journal   (Followers: 8)
SIAM Review     Hybrid Journal   (Followers: 6)
SILICON     Hybrid Journal  
Sistemas & Telemática     Open Access   (Followers: 1)
Sleep and Biological Rhythms     Hybrid Journal   (Followers: 6)
Small     Hybrid Journal   (Followers: 11)
Smart Grid     Open Access  
Soft Computing     Hybrid Journal   (Followers: 8)
Software Engineering, IEEE Transactions on     Hybrid Journal   (Followers: 57)
Soil Dynamics and Earthquake Engineering     Hybrid Journal   (Followers: 14)
Soldagem & Inspeção     Open Access  
Solid-State Circuits Magazine, IEEE     Hybrid Journal   (Followers: 10)
SourceOCDE Developpement urbain, rural et regional     Full-text available via subscription   (Followers: 1)
SourceOCDE Energie     Full-text available via subscription  
SourceOECD Energy     Full-text available via subscription  
SourceOECD Science and Technology Statistics - SourceOCDE Base de donnees des sciences et de la technologie     Full-text available via subscription  
SourceOECD Transport     Full-text available via subscription   (Followers: 3)
SourceOECD Urban, Rural and Regional Development     Full-text available via subscription   (Followers: 1)
South African Computer Journal     Full-text available via subscription  
South African Journal of Agricultural Extension     Open Access   (Followers: 4)
South African Journal of Science     Open Access   (Followers: 3)
Sports Engineering     Hybrid Journal   (Followers: 3)
Stahlbau     Hybrid Journal   (Followers: 3)
Steel in Translation     Hybrid Journal  
Steel Research International     Hybrid Journal   (Followers: 25)
Stochastic Analysis and Applications     Hybrid Journal   (Followers: 2)
Stochastic Processes and their Applications     Hybrid Journal   (Followers: 5)
Stochastics and Dynamics     Hybrid Journal  
Strain     Hybrid Journal   (Followers: 2)
Strategic Planning for Energy and the Environment     Hybrid Journal   (Followers: 4)
Studies in Engineering and Technology     Open Access  
Studies in Interface Science     Full-text available via subscription   (Followers: 1)
Studies in Logic and Practical Reasoning     Full-text available via subscription  
Studies in Surface Science and Catalysis     Full-text available via subscription   (Followers: 1)
Superconductor Science and Technology     Hybrid Journal   (Followers: 2)
Surface Engineering     Hybrid Journal   (Followers: 4)
Surface Review and Letters     Hybrid Journal   (Followers: 1)
Surface Science Reports     Full-text available via subscription   (Followers: 15)
Survey Review     Hybrid Journal   (Followers: 6)
Surveying and Land Information Science     Full-text available via subscription   (Followers: 2)
Sustainability Science     Hybrid Journal   (Followers: 9)
Sustainability Science and Engineering     Full-text available via subscription   (Followers: 5)
Sustainable Management of Sediment Resources     Full-text available via subscription  
Swiss Journal of Geosciences     Hybrid Journal  
Symmetry     Open Access  
Synthesis Lectures on Algorithms and Software in Engineering     Full-text available via subscription   (Followers: 2)
Synthesis Lectures on Antennas     Full-text available via subscription   (Followers: 5)
Synthesis Lectures on Biomedical Engineering     Full-text available via subscription  
Synthesis Lectures on Computational Electromagnetics     Full-text available via subscription   (Followers: 4)
Synthesis Lectures on Energy and the Environment: Technology, Science, and Society     Full-text available via subscription   (Followers: 2)
Synthesis Lectures on Engineering     Full-text available via subscription  
Synthesis Lectures on Global Engineering     Full-text available via subscription  
Synthesis Lectures on Professionalism and Career Advancement for Scientists and Engineers     Full-text available via subscription   (Followers: 1)
Synthetic Metals     Hybrid Journal   (Followers: 4)
Systems Engineering     Hybrid Journal   (Followers: 6)
Systems Engineering Procedia     Open Access  
Systems Research Forum     Hybrid Journal  
Systems Science & Control Engineering     Open Access   (Followers: 5)
Technological Engineering     Open Access  
Technologies     Open Access   (Followers: 1)
TECHNOLOGY     Hybrid Journal  
Technology and Innovation     Full-text available via subscription   (Followers: 3)
Technology in Society     Hybrid Journal   (Followers: 4)
Technometrics     Full-text available via subscription   (Followers: 6)
Tecnologia, Ciencia, Educacion     Open Access   (Followers: 1)
Tecnura     Open Access  
Telecommunications Policy     Hybrid Journal   (Followers: 29)
Terahertz Science and Technology, IEEE Transactions on     Hybrid Journal   (Followers: 2)
Textile Science and Technology     Full-text available via subscription   (Followers: 3)
The Journal of Supercomputing     Hybrid Journal   (Followers: 1)
The Scientific World Journal     Open Access  
Theoretical and Computational Fluid Dynamics     Hybrid Journal   (Followers: 13)
Theoretical Issues in Ergonomics Science     Hybrid Journal   (Followers: 3)
Thermal Engineering     Hybrid Journal   (Followers: 7)
Tikrit Journal of Engineering Science     Open Access  
tm - Technisches Messen     Hybrid Journal   (Followers: 2)
Topics in Catalysis     Hybrid Journal   (Followers: 1)
Traffic Injury Prevention     Hybrid Journal   (Followers: 61)
TRANSACTIONS of the VŠB - Technical University of Ostrava, Safety Engineering Series     Open Access   (Followers: 1)
Transactions of Tianjin University     Full-text available via subscription  
Transport and Telecommunication Journal     Open Access   (Followers: 4)
Transport World Africa     Full-text available via subscription   (Followers: 3)
Transportation Research Record : Journal of the Transportation Research Board     Full-text available via subscription   (Followers: 34)
Transportmetrica A : Transport Science     Hybrid Journal   (Followers: 5)
Trends in Applied Sciences Research     Open Access   (Followers: 1)
Tribology in Industry     Open Access   (Followers: 1)
Tribology International     Hybrid Journal   (Followers: 41)
Tribology Letters     Hybrid Journal   (Followers: 5)
Tribology Transactions     Hybrid Journal   (Followers: 33)
Ultramicroscopy     Hybrid Journal   (Followers: 2)
Uludağ University Journal of The Faculty of Engineering     Open Access  
Universal Journal of Applied Science     Open Access   (Followers: 2)
Universal Journal of Engineering Science     Open Access   (Followers: 1)
Utilities Policy     Hybrid Journal   (Followers: 2)
Vacuum     Hybrid Journal   (Followers: 12)
Virtual and Physical Prototyping     Hybrid Journal   (Followers: 3)
Visualization in Engineering     Open Access  
Walailak Journal of Science and Technology     Open Access  
Waste and Biomass Valorization     Hybrid Journal   (Followers: 1)
Waste Management Series     Full-text available via subscription   (Followers: 2)
Waves in Random and Complex Media     Hybrid Journal  
Waves, Wavelets and Fractals     Open Access  
Wear     Hybrid Journal   (Followers: 28)
Welding in the World     Hybrid Journal   (Followers: 3)
West African Journal of Industrial and Academic Research     Open Access   (Followers: 1)
Women in Engineering Magazine, IEEE     Full-text available via subscription   (Followers: 12)
World Journal of Engineering     Full-text available via subscription   (Followers: 3)
World Journal of Engineering and Technology     Open Access  
World Journal of Environmental Engineering     Open Access   (Followers: 2)
World Pumps     Full-text available via subscription   (Followers: 2)
World Science and Technology     Full-text available via subscription   (Followers: 1)
ZDM     Hybrid Journal  
Zede Journal     Open Access  
Zeitschrift fur Energiewirtschaft     Hybrid Journal  

  First | 1 2 3 4 5 6 | Last

Journal Cover Journal of Electronic Testing
  [SJR: 0.372]   [H-I: 27]   [2 followers]  Follow
   Hybrid Journal Hybrid journal (It can contain Open Access articles)
   ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
   Published by Springer-Verlag Homepage  [2340 journals]
  • A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip
    • Authors: Biswajit Bhowmik; Jatindra Kumar Deka; Santosh Biswas
      Pages: 227 - 254
      Abstract: Abstract With the continuous growth in technology, the role of nano-electronic systems is rapidly expanding in every facet of modern life. Subsequently, the demand of high performance computations and communications by many applications in order to interact with environment and users has become a compulsion. Traditional integrated circuit-based systems, e.g., bus-based systems-on-chip (SoCs), as a consequence are turned into networks- on-chips (NoCs) because of the communication bottleneck by the SoCs. Though, the NoCs visibly move the concern and meet the requirements by the applications but fabricating such NoCs without any defect in channels or logics has eventually evolved into a major challenge. Indeed, one of the major demand nowadays for such systems is to design a time-efficient mechanism for the pre- and post-manufacturing testing of NoC functional components, in order to guarantee outgoing quality while not sacrificing yield and reliability. This paper presents a cost effective and distributed on-line test mechanism that addresses channel-shorts in NoC-based systems. The proposed mechanism detects and diagnoses both intra- and inter-channel short faults. The test mechanism additionally targets transient and stuck-at faults in channels. A convenient test scheduling and energy model are presented. The scheduling scheme offers constant test time with little hardware area and performance overheads on the NoCs irrespective of their topologies and sizes. The proposed test solution is evaluated with fault injection campaign in channels of a set of NoC architectures. Fault simulation detects all modeled faults in channels resulting 100% test and fault coverage metrics. On-line evaluation of the proposed solution reveals insights of the effect of channel-shorts on various performance metrics at large amount of traffic. Furthermore, the proposed solution improves various quality metrics on the set of NoCs, for instance, the test area overhead is reduced up to 28% while the proposed model becomes 16 × faster. Also, improvement on the performance overhead is noticed. The packet latency for instance, is improved by 14.98–50.67% while packet flit energy consumption is reduced by 6.83–43.89%. Such improvements are found to grow with NoC size.
      PubDate: 2017-04-01
      DOI: 10.1007/s10836-017-5655-z
      Issue No: Vol. 33, No. 2 (2017)
  • Test Planning for Core-based Integrated Circuits under Power Constraints
    • Authors: Breeta SenGupta; Dimitar Nikolov; Urban Ingelsson; Erik Larsson
      Pages: 7 - 23
      Abstract: Abstract This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time.
      PubDate: 2017-02-01
      DOI: 10.1007/s10836-016-5638-5
      Issue No: Vol. 33, No. 1 (2017)
  • Fast and Automated Electromigration Analysis for CMOS RF PA Design
    • Authors: Junjie Gu; Haipeng Fu; Weicong Na; Qijun Zhang; Jianguo Ma
      Pages: 133 - 140
      Abstract: Abstract This paper presents fast and automated electromigration (EM) reliability modeling by using automated modeling generation (AMG) algorithm. The AMG converts human based EM modeling into an automated modeling and simulation process with the help of ANSYS parametric design language (APDL) program. For automating the neural model training process, training-driven adaptive sampling is applied to integrate data generation, data distributions determination, model structure adaptation, training and testing into a unified framework. Fully automated reliability model construction and simulation is achieved for the first time. This method effectively shortens the period of EM modeling by using dynamic sampling method. Furthermore, the heat generation from active devices has been considered to describe the heat effect on the interconnect reliability. Through the proposed technique, the allowable sizes, temperature and output power of a CMOS radio frequency power amplifier (RF PA) are derived to give reliability criteria for PA designer.
      PubDate: 2017-02-01
      DOI: 10.1007/s10836-016-5639-4
      Issue No: Vol. 33, No. 1 (2017)
  • A Bridged Contactless Measurement Technique for LC Tank Based
           Voltage-Controlled Oscillator
    • Authors: Zhe Liu; Xiao-Peng Yu; Teng-long Fan; Cheng Cao; Wen-Quan Sui
      Abstract: Abstract This paper presents a bridged contactless measurement technique that can measure the resonant frequency and quality factor of a fully-integrated powered off voltage-controlled oscillator (VCO). Unlike the use of the conventional two-coil inductive link, the proposed technique uses an additional inductor to bridge the coupling between the LC tank and the external inductor serving measurement purposes. This makes it possible to examine the on-chip high frequency oscillator with an off-chip inductor at Printed Circuit Board (PCB) level. As an example, a K-band VCO as well as the proposed test structure have been designed and simulated using 0.13 μm CMOS technology. The quality factor and operating frequency of the oscillator are measured using the proposed contactless technique through extraction from the frequency response of a bridged inductive link. The efficiency of the method has been validated by full wave electromagnetic simulation. As a reference, the characterization of the oscillator is also obtained using the Cadence Spectre RF and Mentor Graphic’s Calibre PEX commercial Electronic Design Automation (EDA) software. The results of these two solutions agree considerably well, which supports the feasibility and potentials of using this technique for contactless measurements.
      PubDate: 2017-03-28
      DOI: 10.1007/s10836-017-5657-x
  • A Parallel Test Application Method towards Power Reduction
    • Authors: Ding Deng; Yang Guo; Zhentao Li
      Abstract: Abstract As the serial scan design has been one of the most popular methods in VLSI circuit test, power consumption during test increases significantly because of its inherent shift mode. To solve this problem, this paper proposes a novel test scheme, which makes a few improvements in the traditional scan architecture and adopts a new two-phase approach. First, each clock chain is activated in turn and the vectors for scan cells in the activated chain are applied in parallel within a test clock period. Second, after one pattern has been applied completely, all chains are activated to capture the response altogether. In addition, a compression algorithm is proposed to augment the parallelism of our method. Experimental results on benchmark circuits and industrial modules show that, compared with the traditional serial scan scheme, the proposed approach can reduce average power by 88.98% and peak power by 59.99% at acceptable area and wire length cost.
      PubDate: 2017-03-25
      DOI: 10.1007/s10836-017-5656-y
  • Editorial
    • Authors: Vishwani D. Agrawal
      PubDate: 2017-03-21
      DOI: 10.1007/s10836-017-5654-0
  • Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency
    • Authors: Vijay Sheshadri; Vishwani D. Agrawal; Prathima Agrawal
      Abstract: Abstract With shrinking device sizes, System-on-Chip (SoC) cores are growing in number and complexity. This has led to high volumes of test data and long test times. Therefore, reducing test cost by minimizing the overall test time is one of the main goals of SoC testing. To efficiently manage test resources and power dissipation, tests for the SoC cores are arranged into test schedules. Traditional SoC test methods assume a constant test frequency and supply voltage (V D D ) for the entire test schedule. However, test power and test time can be regulated by varying V D D and test clock frequency to optimize SoC test schedules for a given power budget. The research presented in this paper focuses on power-aware optimization of SoC test schedules to minimize test time by scaling the supply voltage and test clock rate. This scaling can be on a per session basis (in case of session-based test schedules) or dynamically (in case of sessionless test schedules). Exact and heuristic algorithms for solving the optimization problem are discussed. These algorithms are implemented and applied to several SoC benchmarks. Results show a significant reduction in SoC test time over the conventional test schedules where V D D and clock are fixed at given nominal values.
      PubDate: 2017-03-15
      DOI: 10.1007/s10836-017-5652-2
  • Link Testing: a Survey of Current Trends in Network on Chip
    • Authors: Babak Aghaei; Ahmad Khademzadeh; Midia Reshadi; Kambiz Badie
      Abstract: Abstract As an excellent interconnection model, Network on chip (NoC) addresses different on-chip communication problems and can meet different requirements of performance, cost and reliability. Currently, with the growth of technology practice, wire-based interconnections are more and more unreliable. Consequently, growing sources of unreliability directly impact upon both signals and wires leading to some kinds of while misbehaviors in wires called faults. The literature offers various mechanisms designed for detection and diagnosis of such faults. However, this current paper aims to comprehensively survey these various state of art mechanisms of designed for detection and diagnosis of such faults and discusses them in detail in a way that is quite novel, not found in the previous publications. This is the pioneering survey paper which is concerned with classifying link testing approaches in two Online and Offline categories and extracts some conceptualizations to assist the research community. Besides making comparison among various link testing mechanisms on different parameters in the typical comparative table, detailed explanations are also presented about these parameters in NoC architecture.
      PubDate: 2017-03-10
      DOI: 10.1007/s10836-017-5646-0
  • VI-Based Measurement System Focusing on Space Applications
    • Authors: L. E. Seixas; S. Finco; S. P. Gimenez
      Abstract: Abstract This article describes in detail a custom, high-performance, compact, flexible and reconfigurable test equipment. This measurement system is able to perform, locally or remotely, the electrical characterization of semiconductor devices and integrated circuits (ICs) under ionizing irradiation tests. This measurement platform can be managed remotely through serial, Local Network Area (LAN) link, allowing the electrical characterization of these devices in harsh test environments. Using this customized test measurement system, we were capable to reduce total test time by 1/3 in our TID test application.
      PubDate: 2017-03-07
      DOI: 10.1007/s10836-017-5651-3
  • A Systematic Method for Arranging Diagnostic Tests in Linear Analog DC and
           AC Circuits
    • Authors: Michał Tadeusiewicz; Stanisław Hałgas
      Abstract: Abstract The paper deals with multiple soft fault diagnosis of linear analog circuits. The basic problem of arranging diagnostic tests performed in DC or AC states is considered in detail. A systematic method is developed that allows finding values of the sources applied to the excitation nodes as well as the measurement nodes at which the voltage variations due to the parameter deviations are sufficiently large. For this purpose the sensitivity analysis and the nonlinear programming technique, with appropriate objective function and constraints, are used. Four numerical examples reveal effectiveness of the proposed method for arranging the diagnostic tests.
      PubDate: 2017-03-06
      DOI: 10.1007/s10836-017-5650-4
  • Test Technology Newsletter
    • PubDate: 2017-02-28
      DOI: 10.1007/s10836-017-5653-1
  • Reliability Model for Multiple-Error Protected Static Memories
    • Authors: Hadi Jahanirad
      Abstract: Abstract The problem of multi-cell upset (MCU) becomes a major issue in the nanometer SRAM chips. Various types of multi-bit error correction codes (MECC) have been developed to mitigate this problem. Proper selection of different parameters of each MECC scheme can lead to efficient encoder/decoder design. In this paper a semi-analytical model is presented which can estimate the memory failure probability (as well as mean time between failures (MTBF) and reliability) and can guide the system designers to select proper protection scheme for the system memories. The model was validated by comparison to simulation method (less than 3.1% estimation error) and a state of the art model (less than 2.9% estimation error). The impact of various parameters of four types of correction schemes is analyzed and a comparison of these coding schemes with respect to their capabilities to enhance memory reliability is performed.
      PubDate: 2017-02-28
      DOI: 10.1007/s10836-017-5649-x
  • Multi-Directional Space Tessellation to Improve the Decision Boundary in
           Indirect Mixed-Signal Testing
    • Authors: Álvaro Gómez-Pau; Luz Balado; Joan Figueras
      Abstract: Abstract One of the most challenging aspects in nowadays microelectronics industry is production test and verification of mixed-signal circuits. In order to cope with some of the drawbacks encountered in this scenario, researchers have found alternate test as a promising solution in achieving such endeavor. This work prospects the possibilities of using space tessellations along multiple directions in order to improve the test decision boundary definition in the alternate measure space. The proposed method is able to reduce false positive test outcomes, i.e. test escapes, with acceptable penalty in test yield loss metric. The key idea presented in this work is to use an ensemble of octrees, each of them tessellating the plane along different directions. Such tessellations create a refinement in the non linear test decision boundaries without the need of including extra circuit samples. The tree ensemble, together with a strict test decision criterion, serve as a classifier during the production testing phase. The proposed multi-directional ensemble tessellation strategy has been applied to test a band-pass Biquad filter affected by parametric variations. The proposed method has reported promising simulation results in lowering the test escapes metric as compared to a single octree classifier. The computational overhead of evaluating several octrees is insignificant since 2 n -tree data structures are traversed efficiently. The octree ensemble technique has also been compared against a classic specification guard-banding technique reporting better test yield loss metrics for the same test escape target.
      PubDate: 2017-02-20
      DOI: 10.1007/s10836-017-5648-y
  • A Passive Authentication System Based on Optical Variable
    • Authors: Jasbir N. Patel; Hao Jiang; Bozena Kaminska
      Abstract: Abstract A new optical authentication and security system using optical variable nano/micro-structures (OVNs) is presented. The proposed design features a passive authentication method using a simple optical system found in common fabrication facilities. The passive authentication is obtained by insertion of an OVN image directly on a processing layer or divided between multiple layers of the fabrication process. Authentic fabrication process is validated when the proper alignment (reconstructed image, for example) at the end of the fabrication is achieved. Simple proof-of-concept devices with the OVN-based authentication system are presented along with the optical images of the resulting authentication patterns.
      PubDate: 2017-02-15
      DOI: 10.1007/s10836-017-5645-1
  • Total Ionizing Dose Effect and Single Event Burnout of VDMOS with
           Different Inter Layer Dielectric and Passivation
    • Authors: Jiongjiong Mo; Hua Chen; Liping Wang; Faxin Yu
      Abstract: Abstract In this paper, Total Ionizing Dose (TID) and Single Event Burnout (SEB) effects are investigated on self-developed power VDMOS devices with breakdown voltage (BV) of 200 V. Different inter layer dielectrics (ILD) including Borophosphosilicate glass (BPSG) and Si3N4, and different passivation layers including Si3N4 and SiO2 are tested to evaluate their radiation hardness. The TID results indicate that the threshold voltage VTH of VDMOS is negatively shifted after radiation, and can barely be recovered by post TID annealing. As an ILD layer, Si3N4 is proved to be better than BPSG with less VTH shift. Passivation layer can also influence the TID hardness, which increases with the layer thickness. Heavy ion radiation tests indicate that the devices with different ILD and passivation designs can barely influence the SEB effects. All tested devices with normal breakdown voltage of 200 V cannot survive at VDS more than 80 V under heavy ion radiation.
      PubDate: 2017-02-13
      DOI: 10.1007/s10836-017-5647-z
  • Editorial
    • Authors: Vishwani D. Agrawal
      PubDate: 2017-01-21
      DOI: 10.1007/s10836-017-5644-2
  • Test Technology Newsletter
    • PubDate: 2017-01-17
      DOI: 10.1007/s10836-017-5641-5
  • A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively
           Harden Logic Circuits
    • Authors: I. Wali; B. Deveautour; Arnaud Virazel; A. Bosio; P. Girard; M. Sonza Reorda
      Abstract: Abstract Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.
      PubDate: 2017-01-11
      DOI: 10.1007/s10836-017-5640-6
  • Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal
           Rad-SPICE MOSFET Model
    • Authors: Konstantin O. Petrosyants; Lev M. Sambursky; Igor A. Kharitonov; Boris G. Lvov
      Abstract: Abstract The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.
      PubDate: 2017-01-10
      DOI: 10.1007/s10836-016-5635-8
  • High Speed Energy Efficient Static Segment Adder for Approximate Computing
    • Authors: R . Jothin; C. Vasanthanayaki
      Abstract: Abstract Real time high quantity digital data computing design needs to achieve high performance with required accuracy range. The constraints involved with high performance are low power consumption, area efficiency and high speed. This paper proposes a design of high speed energy efficient Static Segment Adder (SSA), which improves the overall performance based on static segmentation. Accuracy Adjustment Logic (AAL) is incorporated to improve the accuracy derived from negating lower order bytes of input operands. In this paper, an integration of static segment method and accuracy adjustment logic is used to achieve computational accuracy for error tolerant applications. The proposed adder design enables to provide high speed and energy efficiency through the static segmentation method. Image enhancement operation is carried out using proposed SSA design. In this method, 99.4% overall computational accuracy for 16-bit addition even with 8-bit adder can be achieved.
      PubDate: 2017-01-07
      DOI: 10.1007/s10836-016-5634-9
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