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  Subjects -> ENGINEERING (Total: 1957 journals)
    - CHEMICAL ENGINEERING (150 journals)
    - CIVIL ENGINEERING (146 journals)
    - ELECTRICAL ENGINEERING (84 journals)
    - ENGINEERING (1124 journals)
    - ENGINEERING MECHANICS AND MATERIALS (284 journals)
    - HYDRAULIC ENGINEERING (43 journals)
    - INDUSTRIAL ENGINEERING (53 journals)
    - MECHANICAL ENGINEERING (73 journals)

ENGINEERING (1124 journals)            First | 2 3 4 5 6 7 8 9 | Last

International Journal of Innovation Science     Full-text available via subscription   (5 followers)
International Journal of Integrated Engineering     Open Access   (1 follower)
International Journal of Intelligent Engineering Informatics     Hybrid Journal  
International Journal of Intelligent Systems and Applications in Engineering     Open Access   (1 follower)
International Journal of Lifecycle Performance Engineering     Hybrid Journal  
International Journal of Machine Tools and Manufacture     Hybrid Journal   (4 followers)
International Journal of Manufacturing Research     Hybrid Journal   (7 followers)
International Journal of Manufacturing Technology and Management     Hybrid Journal   (10 followers)
International Journal of Materials and Product Technology     Hybrid Journal   (4 followers)
International Journal of Mathematical Education in Science and Technology     Hybrid Journal   (6 followers)
International Journal of Mathematics in Operational Research     Hybrid Journal   (1 follower)
International Journal of Medical Engineering and Informatics     Hybrid Journal   (5 followers)
International Journal of Micro Air Vehicles     Full-text available via subscription   (2 followers)
International Journal of Microwave and Wireless Technologies     Hybrid Journal   (1 follower)
International Journal of Microwave Science and Technology     Open Access   (3 followers)
International Journal of Mobile Network Design and Innovation     Hybrid Journal   (3 followers)
International Journal of Multiphase Flow     Hybrid Journal   (2 followers)
International Journal of Nanomanufacturing     Hybrid Journal   (1 follower)
International Journal of Nanoscience     Hybrid Journal   (1 follower)
International Journal of Nanotechnology     Hybrid Journal   (4 followers)
International Journal of Navigation and Observation     Open Access   (4 followers)
International Journal of Network Management     Hybrid Journal  
International Journal of Nonlinear Sciences and Numerical Simulation     Full-text available via subscription   (1 follower)
International Journal of Numerical Methods for Heat & Fluid Flow     Hybrid Journal   (6 followers)
International Journal of Optics     Open Access   (1 follower)
International Journal of Organisational Design and Engineering     Hybrid Journal   (7 followers)
International Journal of Pattern Recognition and Artificial Intelligence     Hybrid Journal   (6 followers)
International Journal of Pavement Engineering     Hybrid Journal   (2 followers)
International Journal of Physical Modelling in Geotechnics     Hybrid Journal   (2 followers)
International Journal of Plasticity     Hybrid Journal   (6 followers)
International Journal of Plastics Technology     Hybrid Journal  
International Journal of Polymer Analysis and Characterization     Hybrid Journal   (2 followers)
International Journal of Polymer Science     Open Access   (15 followers)
International Journal of Precision Engineering and Manufacturing     Hybrid Journal   (8 followers)
International Journal of Precision Technology     Hybrid Journal  
International Journal of Pressure Vessels and Piping     Hybrid Journal   (2 followers)
International Journal of Production Economics     Hybrid Journal   (10 followers)
International Journal of Quality and Innovation     Hybrid Journal   (2 followers)
International Journal of Quality Engineering and Technology     Hybrid Journal   (2 followers)
International Journal of Quantum Information     Hybrid Journal  
International Journal of Rapid Manufacturing     Hybrid Journal   (4 followers)
International Journal of Reliability, Quality and Safety Engineering     Hybrid Journal   (4 followers)
International Journal of Renewable Energy Technology     Hybrid Journal   (7 followers)
International Journal of Robust and Nonlinear Control     Hybrid Journal   (2 followers)
International Journal of Science Engineering and Advance Technology     Open Access  
International Journal of Sediment Research     Full-text available via subscription   (1 follower)
International Journal of Self-Propagating High-Temperature Synthesis     Hybrid Journal   (2 followers)
International Journal of Signal and Imaging Systems Engineering     Hybrid Journal  
International Journal of Six Sigma and Competitive Advantage     Hybrid Journal  
International Journal of Social Robotics     Hybrid Journal   (1 follower)
International Journal of Software Engineering and Knowledge Engineering     Hybrid Journal   (1 follower)
International Journal of Space Science and Engineering     Hybrid Journal   (2 followers)
International Journal of Speech Technology     Hybrid Journal   (2 followers)
International Journal of Spray and Combustion Dynamics     Full-text available via subscription   (5 followers)
International Journal of Surface Engineering and Interdisciplinary Materials Science     Full-text available via subscription   (1 follower)
International Journal of Surface Science and Engineering     Hybrid Journal   (7 followers)
International Journal of Sustainable Engineering     Hybrid Journal   (7 followers)
International Journal of Sustainable Manufacturing     Hybrid Journal   (4 followers)
International Journal of Systems Assurance Engineering and Management     Hybrid Journal  
International Journal of Systems, Control and Communications     Hybrid Journal   (2 followers)
International Journal of Technology Management and Sustainable Development     Hybrid Journal   (1 follower)
International Journal of Technology Policy and Law     Hybrid Journal   (3 followers)
International Journal of Telemedicine and Applications     Open Access   (2 followers)
International Journal of Thermal Sciences     Hybrid Journal   (4 followers)
International Journal of Thermodynamics     Open Access   (1 follower)
International Journal of Turbo & Jet-Engines     Full-text available via subscription  
International Journal of Ultra Wideband Communications and Systems     Hybrid Journal  
International Journal of Vehicle Autonomous Systems     Hybrid Journal  
International Journal of Vehicle Design     Hybrid Journal   (5 followers)
International Journal of Vehicle Information and Communication Systems     Hybrid Journal   (1 follower)
International Journal of Vehicle Noise and Vibration     Hybrid Journal   (2 followers)
International Journal of Vehicle Safety     Hybrid Journal   (3 followers)
International Journal of Vehicular Technology     Open Access   (1 follower)
International Journal of Virtual Technology and Multimedia     Hybrid Journal   (4 followers)
International Journal of Wavelets, Multiresolution and Information Processing     Hybrid Journal  
International Journal on Artificial Intelligence Tools     Hybrid Journal   (4 followers)
International Nano Letters     Open Access   (5 followers)
International Review of Applied Sciences and Engineering     Full-text available via subscription  
Inverse Problems in Science and Engineering     Hybrid Journal   (3 followers)
Ionics     Hybrid Journal  
IPTEK The Journal for Technology and Science     Open Access  
IRBM News     Full-text available via subscription  
Ironmaking & Steelmaking     Hybrid Journal   (2 followers)
Irrigation and Drainage Systems     Hybrid Journal  
ISA Transactions     Full-text available via subscription  
ISRN Communications and Networking     Open Access   (4 followers)
ISRN Nanotechnology     Open Access  
ISRN Signal Processing     Open Access  
ISRN Thermodynamics     Open Access  
ISRN Tribology     Open Access  
IT Professional     Full-text available via subscription   (1 follower)
Journal of Biosensors & Bioelectronics     Open Access   (1 follower)
Journal of Advanced Manufacturing Systems     Hybrid Journal   (8 followers)
Journal of Aerosol Science     Hybrid Journal   (2 followers)
Journal of Aerospace Engineering     Full-text available via subscription   (73 followers)
Journal of Alloys and Compounds     Hybrid Journal   (6 followers)
Journal of Analytical and Applied Pyrolysis     Hybrid Journal   (3 followers)
Journal of Analytical Science & Technology     Open Access   (4 followers)
Journal of Analytical Sciences, Methods and Instrumentation     Open Access   (1 follower)
Journal of Applied Analysis     Full-text available via subscription  

  First | 2 3 4 5 6 7 8 9 | Last

Journal of Electronic Testing    [3 followers]  Follow    
  Hybrid Journal Hybrid journal (It can contain Open Access articles)
     ISSN (Print) 1573-0727 - ISSN (Online) 0923-8174
     Published by Springer-Verlag Homepage  [2187 journals]   [SJR: 0.424]   [H-I: 22]
  • A Comprehensive Framework for Counterfeit Defect Coverage Analysis and
           Detection Assessment
    • Abstract: Abstract The increasing threat of counterfeit electronic components has created specialized service of testing, detection, and avoidance of such components. However, various types of counterfeit components – recycled, remarked, overproduced, defective, cloned, forged documentation, and tampered – pose serious threats to supply chain. Over the past few years, standards and programs have been put in place throughout the supply chain that outline testing, documenting, and reporting procedures. However, there is little uniformity in the test results among the various entities. Currently, there are no metrics for evaluating these counterfeit detection methods. In this paper, we have developed a detailed taxonomy of defects present in counterfeit components. Based on this taxonomy, a comprehensive framework has been developed to find an optimum set of detection methods considering test time, test cost, and application risks. We have also performed an assessment of all the detection methods based on the newly introduced metrics – counterfeit defect coverage, under-covered defects, and not-covered defects.
      PubDate: 2014-01-15
       
  • A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction
           of 3D Wafer-on-Wafer Stacked ICs
    • Abstract: Abstract Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, compact device dimension, etc. Wafer-on-wafer stacking offers practical advantages in 3D IC fabrication, but it suffers from low compound yield. To improve the yield, a novel manipulation scheme of wafer named n-sector symmetry and cut (SSCn) is proposed. In this method, wafers with rotational symmetry are cut into n identical sectors, where n is a suitably chosen integer. The sectors are then used to replenish repositories. The SSCn method is combined with best-pair matching algorithm for compound yield evaluation. Simulation of wafers with nine different defect distributions shows that previously known plain rotation of wafers offers only a trivial benefits in yield. A cut number four is optimal for most of the defect models. The SSC4 provides significantly higher yield and the advantage becomes more obvious with increase of the repository size and the number of stacked layers. Cost model of SSCn is analyzed and the cost-effectiveness of SSC4 is established. Observations made are: 1) Cost benefits of SSC4 become larger as the manufacturing overhead of SSC4 become smaller, 2) cost improvement of SSC4 over conventional basic method increases as the number of stacked layers increases and 3) for most defect models, SSC4 largely reduces the cost even when manufacturing overhead of SSC4 is considered to be very large.
      PubDate: 2014-01-12
       
  • Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using
           Heavy Ion, Proton, and Pulsed Laser
    • Abstract: Abstract This paper discusses multiple methods of Single-Event Transient (SET) measurements on a commercial DC/DC Pulse Width Modulator (PWM). Heavy ion, proton, and pulsed laser are used in the experiments. The correlations between the heavy ion, pulsed laser and proton data are analyzed and presented. A proton cross-section model is used to derive proton cross-section from heavy ion test data. The calculated result is close to the real proton data, which means the heavy ion and proton data fit well. The relationship between pulsed laser and proton are also analyzed through heavy as a medium.
      PubDate: 2014-01-09
       
  • Clock Faults Induced Min and Max Delay Violations
    • Abstract: Abstract In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.
      PubDate: 2013-12-15
       
  • Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via
           Electro-Thermal Coupling
    • Abstract: Abstract A differential temperature sensor for on-chip signal and DC power monitoring is presented for built-in testing and calibration applications. The amplifiers in the sensor are designed with class AB output stages to extend the dynamic range of the temperature/power measurements. Two high-gain amplification stages are used to achieve high sensitivity to temperature differences at points close to devices under test. Designed in 0.18 μm CMOS technology, the sensor has a simulated sensitivity that is tunable up to 210 mV/°C with a corresponding dynamic range of 13 °C. The sensor consumes 2.23 mW from a 1.8 V supply. A low-power version of the sensor was designed that consumes 1.125 mW from a 1.8 V supply, which has a peak sensitivity of 185.7 mV/°C over a 8 °C dynamic range.
      PubDate: 2013-12-13
       
  • Simulation Based Framework for Accurately Estimating Dynamic Power-Supply
           Noise and Path Delay
    • Abstract: Abstract Power-supply noise is one of the major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur otherwise under normal operation. Thus, there exists a need to accurately estimate on-chip supply noise early in the design phase to meet power requirements in normal mode and during test to prevent overstimulation during the test cycle and avoid false failures. Simultaneous switching activity (SSA) of several logic components is one of the main sources of power-supply noise (PSN) which results in reduction of supply voltages at the power-supplies of the logic gates. Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. To our knowledge, inductive drop is not included in current noise analysis for simplification. The power delivery networks in today’s very deep-submicron chips are susceptible to slight variations and cause sudden large current spikes leading to higher Ldi ⁄ dt than resistive drop essentiating the need to account for this drop. Power-supply noise also impacts circuit operation incurring a significant increase in path delays. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. Accurate and efficient techniques are required to quantify supply noise and its impact on path delays to ensure reliable operation in both mission mode and during test. We present a scalable current-based dynamic method to estimate both IR and Ldi / dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay. Our technique uses simulations of individual extracted paths in comparison to time-consuming full-chip simulations and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for combinational and sequential benchmark circuits are presented demonstrating the effectiveness of our techniques.
      PubDate: 2013-12-12
       
  • Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield
           Improvement of MEMS Convective Accelerometers
    • Abstract: Abstract In this paper, different strategies for post-silicon yield improvement of MEMS convective accelerometers are explored. A key feature of the proposed strategies is that they can be implemented at low-cost using electrical test equipment since they only rely on the measurement of the relative deviation of Wheatstone bridge impedance due to power dissipation in the heating element. Different electrical test flows are defined that implement either sensitivity binning, sensitivity calibration, or both. Optionally, an additional constraint can be inserted in the test flows in case power consumption performance has also to be satisfied in addition to sensitivity. The efficiency of the different strategies is evaluated and discussed considering a population of 1,000 devices generated through Monte-Carlo simulation. Finally, experimental measurements that validate the calibration principle are presented.
      PubDate: 2013-12-06
       
  • A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime
           Partial Reconfiguration
    • Abstract: Abstract The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today’s FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components – ALU, multiplier-accumulator, and instruction-fetch unit – of an open-source embedded processor.
      PubDate: 2013-12-03
       
  • Survey and Evaluation of Automated Model Generation Techniques for High
           Level Modeling and High Level Fault Modeling
    • Abstract: Abstract It is known that automated model generation (AMG) techniques for linear systems are sufficiently mature to handle linear systems during high level modeling (HLM). Other AMG techniques have been developed for various levels of nonlinear behavior and to focus on specific issues such as high level fault modeling (HLFM). However, no single nonlinear AMG technique exists which can be confidently adapted for any nonlinear system. In this paper, a survey on AMG techniques over the last two decades is conducted. The techniques are classified into two main areas: system identification (SI) based AMG and model order reduction (MOR) based AMG. Overall, the survey reveals that more advanced research for AMG techniques is required to handle strongly nonlinear systems during HLFM.
      PubDate: 2013-12-01
       
  • MoDiVHA: A Hierarchical Strategy for Distributed Test Assignment
    • Abstract: Abstract Distributed diagnosis allows a set of fault-free nodes to monitor the state of all nodes of a given system. Diagnosis is based on the results of tests, which are assigned among system nodes. Hierarchical testing assignments lead to efficient and scalable diagnosis algorithms, both in terms of the number of tests executed, and the latency. In this work we present a novel hierarchical testing strategy, called MoDiVHA. By obtaining as much diagnostic information as possible from each test, and avoiding tests on nodes about which information has been already obtained, MoDiVHA executes less tests in comparison with previously proposed assignments. Experimental results are presented from three series of simulations conducted to compute the number of tests and diagnosis latency for various system sizes and fault situations.
      PubDate: 2013-12-01
       
  • Online Testable Approaches in Reversible Logic
    • Abstract: Abstract We present an overview and analysis of existing work in the design of online testable reversible logic circuits, as well as propose new approaches for the design of such circuits. We explain how previously proposed approaches are unnecessarily high in overhead and in many cases do not provide adequate fault coverage. Proofs of the correctness of our approaches are provided, and discussions of the advantages and disadvantages of each design approach are given. Experimental results comparing our approaches to existing work are presented as well. Both approaches that we propose have better fault coverage and significantly lower overheads than previous approaches.
      PubDate: 2013-12-01
       
  • Editorial
    • PubDate: 2013-11-19
       
  • Preserving Hamming Distance in Arithmetic and Logical Operations
    • Abstract: Abstract This paper presents a new method for fault-tolerant computing where for a given error rate, r, the hamming distance between correct inputs and faulty inputs, as well as the hamming distance between correct results and faulty results, is preserved throughout processing; thereby enabling correction of up to r transient faults per computation cycle. The new method is compared and contrasted with current protection methods and its cost/performance is analyzed.
      PubDate: 2013-11-15
       
  • Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms
    • Abstract: Abstract This paper presents an approach for increasing the lifetime of systems implemented on SRAM-based FPGAs, by introducing fault tolerance properties enabling the system to autonomously manage the occurrence of both transient and permanent faults. On the basis of the foreseen mission time and application environment, the designer is supported in the implementation of a system able to reconfigure itself, either by reloading the correct configuration in case of transient faults, or by relocating part of the functionality in presence of permanent faults. The result is a system implementation offering good performance and correct functionality even when faults occur. The proposed approach is evaluated in a case study to highlight the overall characteristics of the final implementation.
      PubDate: 2013-11-13
       
  • Efficient Test Compression Technique for SoC Based on Block Merging and
           Eight Coding
    • Abstract: Abstract Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time.
      PubDate: 2013-11-07
       
  • Selective SWIFT-R
    • Abstract: Abstract Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.
      PubDate: 2013-11-07
       
  • Effective Timing Error Tolerance in Flip-Flop Based Core Designs
    • Abstract: Abstract Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90 nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach.
      PubDate: 2013-11-07
       
  • Test Technology Newsletter
    • PubDate: 2013-11-06
       
  • Low Cost Time Efficient Multi-tone Test Signal Generation Using OFDM
           Technique
    • Abstract: Abstract In this paper, we present a new multi-tone test signal generation method with different frequency tones uniformly distributed across a wideband spectrum. It employs OFDM (orthogonal frequency-division multiplexing) spread spectrum technique to allow users to define signal parameters with a great flexibility as per the test requirements. This OFDM method essentially starts from the frequency sampling and then conversion to generate time domain signals, which can significantly reduce the number of data points in the signal generation. Response of such test signals from the device under test (DUT) can be captured and analyzed so as to characterize frequency response associated with each frequency tone. For validation, simulations with Matlab Simulink tool and hardware implementation on a Xilinx Virtex5 FPGA board are developed.
      PubDate: 2013-10-26
       
  • Multi-bit Sigma-Delta TDC Architecture with Improved Linearity
    • Abstract: Abstract This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.
      PubDate: 2013-10-04
       
 
 
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