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 Components, Packaging and Manufacturing Technology, IEEE Transactions on   [SJR: 0.62]   [H-I: 23]   [26 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Online) 2156-3950    Published by IEEE  [191 journals]
• IEEE Transactions on Components, Packaging and Manufacturing Technology
publication information
• Abstract: Provides a listing of current staff, committee members and society officers.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• IEEE Components, Packaging, and Manufacturing Technology Society
information for authors
• Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and society editors for this issue of the publication.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• IEEE Components, Packaging, and Manufacturing Technology Society
Information
• Abstract: Presents a listing of the editorial board, board of governors, current staff, committee members, and society editors for this issue of the publication.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Interposer Technologies for High-Performance Applications
Pages: 819 - 828
Abstract: This paper explores the current state of the art in silicon, organic, and glass interposer technologies and their high-performance applications. Issues and challenges broadly encompassing electrical, mechanical, and thermal properties of these interposer technologies are discussed along with the proven and under research solutions pertaining to these challenges. An evaluation of high-performance applications for these three technologies provides a useful insight into the role of interposers for such applications. This paper is an effort to evaluate and compare the viability of silicon, organic, and glass interposer technologies for high-performance applications. This paper also discusses the future trends, promising advancements, and market requirements with special emphasis on glass interposer technologies as evaluated to be the most viable option for the future high-performance applications.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Reliability of Copper Through-Package Vias in Bare Glass Interposers
• Authors: Kaya Demir;Andac Armutlulu;Venky Sundaram;P. Markondeya Raj;Rao R. Tummala;
Pages: 829 - 837
Abstract: Thermomechanical reliability of copper-plated through-package vias (TPVs) in ultrathin bare glass interposers was investigated through modeling, design, fabrication, reliability characterization, and failure analysis. Finite-element models were developed to analyze stress and strain distribution in TPV structures, and to obtain design guidelines for reliable TPVs. In order to experimentally validate the predictions of simulations, bare glass substrates of 100 μm thickness with vias of 30 μm diameter at 120 μm pitch were metallized using Ti/Cu sputtering, followed by patterning and electroplating. Cu TPV daisy chains were fabricated and subjected to thermal cycling test between -55 °C and 125 °C to assess their thermomechanical reliability. Detailed cross-sectional analysis was also carried out by scanning electron microscope imaging of TPV cross sections. No electrical failures were detected in the Cu TPV chains. Failure analysis revealed copper delamination and crack formation in glass. The experimental reliability results are consistent with the thermomechanical models. Design and process recommendations are provided based on the modeling and experimental results.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Embedded Trench Redistribution Layers at 2– $5~\mu \text{m}$ Width and
Space by Excimer Laser Ablation and Surface Planer Processes for 20–
$40~\mu \text{m}$ I/O Pitch Interposers
• Authors: Yuya Suzuki;Habib Hichri;Frank Wei;Venky Sundaram;Rao Tummala;
Pages: 838 - 845
Abstract: This paper reports on one of the first demonstrations of the formation and metallization of 2-5-μm lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, without using chemical mechanical planarization. The trenches and vias in 8-15-μm-thick dry-film dielectrics were formed by 308-nm excimer laser ablation, followed by the metallization of the trenches and vias by copper electrodeposition. A low-cost planarization process was used to remove the copper overburden with a surface planer tool. Using an optimized set of materials and processes, multilayer redistribution layers with 2-5 μm trenches and vias were successfully demonstrated. Although thin film processes on silicon wafers have been able to achieve 40-μm I/O pitch for interposers, the materials and processes integrated in this paper are scalable to large panel fabrication at much higher throughput, for interposers and high-density fanout packaging at lower cost and higher performance than silicon interposers.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• A Digital Signal Processing-Assisted Microfluidic PCB for On-Chip
Fluorescence Detection
• Authors: Sarkis Babikian;G. P. Li;Mark Bachman;
Pages: 846 - 854
Abstract: We report the use of digital signal processing (DSP) strategies to realize high-sensitivity on-chip fluorescence detection in microfluidic-opto-electronic printed circuit board (PCB) devices without requiring bulky high-quality optical components and filters. An isotachophoresis (ITP) assay was studied in a microfluidic PCB with an embedded standard complementary metal oxide semiconductor sensor array demonstrating a detection sensitivity of 10-nm initial concentration for fluorescein. The amplified ITP signal is processed with the DSP algorithms allowing the fluorescence signal extracted from noisy sensor output to achieve high signal-to-noise ratio. The DSP-assisted fluorescence detection system utilizes off-the-shelf, consumer-grade electronics and lensless imaging to achieve high-level but also scalable integration on microfluidic PCBs.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Process Optimization of Pressure-Assisted Rapid Ag Sintering Die Attach
for 300 °C Applications
• Authors: Fang Yu;R. Wayne Johnson;Michael C. Hamilton;
Pages: 855 - 861
Abstract: Ag sintering is a promising die-attach technique to fabricate digital and analog thick-film modules for 300°C applications. In this paper, a low-temperature, pressure-assisted rapid sintering process was developed. Process optimization decreased the sintering time to 1 min, which allowed the use of an FC150 thermocompression flip-chip/die bonder for automated die attach instead of a hydraulic press, improving the manufacturability. The porosity of the sintered Ag layer was decreased from 30% (pressureless assembly) to 15% with the application of a low pressure (7.6 MPa) during the 1-min sintering process for large die. The average shear strength for the 3 × 3-mm2 die was 70.7 MPa, and the 8 × 8-mm2 die could not be sheared off due to the 100-kg force limit of the shear test module. Both Ag and Au metallization (die and substrate) were studied. A new substrate metallization combination was found that was compatible with thick-film Au metallized substrates.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Transient Thermal Analysis of 3-D Integrated Circuits Packages by the DGTD
Method
• Authors: Ping Li;Yilin Dong;Min Tang;Junfa Mao;Li Jun Jiang;Hakan Bağcı;
Pages: 862 - 871
Abstract: Since accurate thermal analysis plays a critical role in the thermal design and management of the 3-D system-level integration, in this paper, a discontinuous Galerkin time-domain (DGTD) algorithm is proposed to achieve this purpose. Such as the parabolic partial differential equation (PDE), the transient thermal equation cannot be directly solved by the DGTD method. To address this issue, the heat flux, as an auxiliary variable, is introduced to reduce the Laplace operator to a divergence operator. The resulting PDE is hyperbolic, which can be further written into a conservative form. By properly choosing the definition of the numerical flux used for the information exchange between neighboring elements, the hyperbolic thermal PDE can be solved by the DGTD together with the auxiliary differential equation. The proposed algorithm is a kind of element-level domain decomposition method, which is suitable to deal with multiscale geometries in 3-D integrated systems. To verify the accuracy and robustness of the developed DGTD algorithm, several representative examples are benchmarked.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Optimal Thermal Conditions for Maximum Power Generation When Operating
Thermoelectric Liquid-to-Liquid Generators
• Authors: Éric V. Sempels;Frédéric J. Lesage;
Pages: 872 - 881
Abstract: Thermoelectric modules (TEMs) embedded in heat exchangers provide a means of converting industrial waste heat into electrical power for local electrical energy needs. Due to the nature of the thermoelectric effect, a generator's efficiency is dictated by a balance in its ability to act as a heat exchanger and its ability to maintain a high temperature difference. The present system-level study investigates the thermal conditions required for optimal power generation when using TEM embedded heat exchangers. From the analytical results, optimal thermal operating conditions are scrutinized, and a model is developed providing insight into the balance between heat transfer and temperature differential for optimal thermoelectric generator (TEG) design. It is demonstrated that under constant temperature difference, a heat exchanger effectiveness of 0.5 is an optimal compromise between heat flux and temperature difference for thermoelectric power generation. This criterion is universally applicable to TEGs as it relies solely on basic heat transfer and thermoelectric equations. Numerical simulations confirm that constant temperature difference along the length of the generator is achievable using tabulated inserts. A generator's efficiency and power output are analytically solved and compared to the experimental results.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Experimental Failure Analysis of a Rear Door Heat Exchanger With Localized
Containment
• Authors: Kourosh Nemati;Husam A. Alissa;Bruce T. Murray;Ken Schneebeli;Bahgat Sammakia;
Pages: 882 - 892
Abstract: The accelerated growth of heat load in high-density data centers presents challenges to the design of effective cooling solutions. Both energy efficiency and the information technology (IT) equipment reliability are key requirements. Localized hybrid air-water cooling systems such as Rear Door Heat eXchangers (RDHXs) are an effective means to achieve these requirements. In this paper, the transient aerodynamic and thermal performance of a commercial RDHX was investigated experimentally. The RDHX was attached to an isolated server cabinet with a controllable heat load. A localized containment system was used to direct the airflow to the equipment in the cabinet that emanates from a single perforated tile within the enclosure. The water flow rate and supply water temperature to the RDHX was controlled, and a grid of 36 air velocity/temperature sensors was employed to monitor the airside of the cooling system. The cooling performance of the RDHX in an air blower failure scenario was investigated. The failure scenario was designed to diminish different parts of the overall system. The impact on the IT equipment and the cabinet outlet temperatures was assessed. Also, there was a significant reduction in the airflow to the IT equipment. The impact of the reduced airflow on different parts of the cabinet as well as the cooling performance of the heat exchanger was characterized during both failure and recovery.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• A Multiphysics Modeling and Experimental Analysis of Pressure Contacts in
Power Electronics Applications
• Authors: Pushpa Rajaguru;Jose Angel Ortiz-Gonzalez;Hua Lu;Chris Bailey;Olawiwola Alatise;
Pages: 893 - 900
Abstract: This paper details a modeling and experimental assessment of the packaging process for a silicon carbide Schottky diode using pressure contacts. The work detailed in this paper is original, as it applies a combined electrothermomechanical modeling analysis to this packaging method supported by experimental validation. A key design objective for this packaging process is to identify suitable contact pad materials, heatsinks, and process variables such as clamping force to meet electrical, thermal, and reliability specifications. Molybdenum and aluminum graphite (ALG) have been identified as two suitable materials for the contact pads. Clamping forces ranging from 300 to 500 N and electric current ranging from 10 to 30 A have been investigated in terms of the resulting electrical and thermal contact resistances, temperatures, and stresses induced across the package. The performance of two heatsink designs with heat dissipation rates of 12893 and 4991 W/m2k has also been investigated. Both the modeling and initial experimental results detailed in this paper show that ALG provides better performance in terms of generating a lower average chip temperature. Both temperature and stress in the diode are predicted as a function of clamping force and load current. This will aid the packaging engineer to identify suitable process parameters to meet junction temperature requirements at different applied load currents.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Analysis of Electrodynamic Forces in Switching Devices for Railway
Applications
• Authors: Alberto Dolara;Francesco Grimaccia;Silvio Zuffetti;
Pages: 901 - 911
Abstract: Nowadays, the railway transport field imposes stringent technological limitations in terms of safety requirements and cost savings, which ask for an accurate design for all the devices installed onboard the trains. Switching devices for railway applications have to be optimized in size, weight, and cost; their accurate design allows to reduce the development costs and time. Moreover, the evaluation of electromagnetic forces acting on the current-carrying parts of switching devices is crucial for their proper operation and sizing, especially referring to movable conductors. This paper provides two methods, namely, an analytical and a numerical one, to evaluate the electrodynamic forces in switching devices with complex-shape circuits. The analytical method is a predesign tool able to evaluate in a fast way the electrodynamic forces on the current-carrying conductors. The numerical tool is a verification model that evaluates the forces generated by currents and flux densities by using a 3-D finite-element method. These methods are here applied to fully analyze a so-called earthing switch for railway application. Numerical results are reported to prove the effectiveness of the proposed methods.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Parasitic Extraction for Heterogeneous Face-to-Face Bonded 3-D ICs
• Authors: Yarui Peng;Taigon Song;Dusan Petranovic;Sung Kyu Lim;
Pages: 912 - 924
Abstract: Face-to-face (F2F)-bonded 3-D ICs provide higher vertical interconnection densities and cost-effective solutions compared to face-to-back-bonded 3-D ICs. With a bumpless direct-copper-bonding process, the die-to-die distance is significantly reduced to enable a finer F2F via pitch. Unfortunately, this increases interdie parasitic components that require careful extraction. Heterogeneous 3-D ICs are built using dies from different design houses and foundries, potentially using different technology nodes. They again require accurate parasitic extraction across multiple dies and thus call for new computer-aided design methodologies with intellectual property protection. We, for the first time, provide a comprehensive study of three full-chip parasitic extraction methods for homogeneous and heterogeneous F2F 3-D ICs. The traditional die-by-die extraction ignores any interdie coupling and underestimates the total coupling capacitance by 35%. The holistic extraction that takes all dies into account provides the most accurate results at the cost of high layout-versus-schematic (LVS) complexity. The in-context extraction, taking only the interface layers from the neighbor dies, offers tradeoffs between accuracy and complexity. Our study shows that with only two interface layers, in-context extraction offers highly accurate and efficient extraction results with 0.9% error for the total ground capacitance and 0.8% for the total coupling capacitance.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Through-Silicon Via Capacitance–Voltage Hysteresis Modeling for
2.5-D and 3-D IC
• Authors: Dong-Hyun Kim;Youngwoo Kim;Jonghyun Cho;Bumhee Bae;Junyong Park;Hyunsuk Lee;Jaemin Lim;Jonghoon J. Kim;Stefano Piersanti;Francesco de Paulis;Antonio Orlandi;Joungho Kim;
Pages: 925 - 935
Abstract: We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input-output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Modeling and Characterization of Coaxial Through-Silicon Via With
Electrically Floating Inner Silicon
• Authors: Wen-Sheng Zhao;Jie Zheng;Jing Wang;Feng Liang;Fei Wen;Linxi Dong;Dingwen Wang;Gaofeng Wang;
Pages: 936 - 943
Abstract: In this paper, coaxial through-silicon via (C-TSV) is modeled and studied with the consideration of electrically floating inner silicon substrate. Nonlinear capacitances of the central via and the outer shielding shell are accurately captured by solving cylindrical Poisson equation. By employing symbolically defined device block, the nonlinear capacitances of the C-TSV with electrically floating inner silicon are combined into the equivalent circuit model, and their impacts on the electrical characteristics are examined.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• A Universal Approach for Designing an Unequal Branch-Line Coupler With
Arbitrary Phase Differences and Input/Output Impedances
• Authors: Yongle Wu;Lingxiao Jiao;Quan Xue;Yuanan Liu;
Pages: 944 - 955
Abstract: For the first time, this paper presents a novel approach for designing a coupler with arbitrary division, optional phase difference, and alternative input/output impedances. In the section of theoretical analysis, rigorous closed-form design equations are derived, and explicit methodology for computer-aided design is given based on the equations. To validate the idea, several numerical examples extracted from the design procedure are constructed and demonstrated. Eventually, three prototypes of the coupler are fabricated, and experiments are carried out. The excellent agreement between the theoretical and experimental results sufficiently verifies the theoretical methodology. This proposed coupler is well applicable to the applications that require high flexibility in couplers' performances.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Design of Compact Bandpass Filters Using Quarter-Mode and Eighth-Mode SIW
Cavities
• Authors: Peng Li;Hui Chu;Ru-Shan Chen;
Pages: 956 - 963
Abstract: The contribution of this paper is to propose novel balanced and dual-band bandpass filters (BPFs), using quarter-mode (QM) and eighth-mode (EM) substrate integrated waveguide (SIW) cavities, for the size reduction of the overall circuit. Two balanced BPFs, which separately demonstrate a third-order Chebyshev response and a fourth-order quasi-elliptic response, are realized by properly choosing, feeding, and coupling those QMSIW and EMSIW cavities. Not only desired differential-mode operation within the passband, but also good common-mode suppression in a certain frequency range have been achieved. Furthermore, a dual-band BPF with improved out-of-band rejection is also realized by properly constructing the coupling topology of four EMSIW cavities. An additional source-to-load coupling path is introduced in this dual-band BPF to obtain more transmission zeros (TZs). The sizes of resonant cavities utilized in the above designs are only one-fourth or one-eighth of those rectangular ones in conventional designs, which lead to a significant reduction in the overall circuit size. All proposed designs have been fabricated and measured to verify simulation predictions. Based on the author's knowledge, it is the first time using QMSIW and EMSIW for balanced filter designs, and dual-band filter designs with TZs.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• A Filtering Dual-Polarized Antenna Subarray Targeting for Base Stations in
Millimeter-Wave 5G Wireless Communications
• Authors: Hui Chu;Yong-Xin Guo;
Pages: 964 - 973
Abstract: A 2×2 dual-polarized antenna subarray with filtering responses is proposed in this paper. This antenna subarray is a multilayered 3-D geometry, including a dual-path 1× 4 feeding network and four cavity-backed slot antennas. The isolation performance between two input ports is greatly improved by a novel method, which only needs to modify several vias in a square resonator. Cavities in the feeding network are properly arranged and coupled using different coupling structures, so that the operation modes in each cavity for different paths can always remain orthogonal, which enables the subarray to exhibit not only filtering functions (in both reflection coefficients and gain responses), but also a low cross-polarization level. A prototype is fabricated with a center frequency of 37 GHz and a bandwidth of 600 MHz for demonstration. Good agreement is achieved between simulation and measurement, for both S-parameter and far-field results. The proposed filtering dual-polarized antenna array is very suitable to be employed as the subarray in millimeter-wave 5G base stations to reduce the complexity and integration loss of such beamforming systems.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Design and Experiment of an Internal Mix Airblast Spray-Coating Valve
• Authors: Hai Jiang;Shoudong Gu;Ruyi Li;Qingqing Lv;Song Lu;Biao Li;Jianfang Liu;
Pages: 974 - 981
Abstract: In order to attain high speed and high precision in modern electronic coating, an internal-mix airblast spray-coating valve was designed. The device used a reciprocating piston to control the supply of liquid, which was mixed with gas in the atomization chamber and was sprayed out from the nozzle. The movement of gas and liquid in the spraying nozzle was first analyzed. The structural parameters of the spraying nozzle are designed and optimized via finite element software. Finally, the experimental platform was set up to test the performance of the optimized spray-coating valve. Results show that supply pressures of atomizing gas and fluid all directly affect the coating layer width and thickness, and that the spraying regularity between them was obtained. When the fluid viscosity, atomizing air pressure, fluid supply pressure, and spraying height were 200 cps, 30 kpa, 20 kpa, and 8 mm, respectively, the rate of the moving platform was 100 mm/s, the length of the coating layer was 100 mm, the coating layer width was 9.4 mm, the coating layer thickness was 230 μm, and the average coating mass was 186 mg. The accuracy of the coating mass can be controlled at less than 5%.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• 3-D Printed Air Substrates for the Design and Fabrication of RF Components
• Authors: Mohd Ifwat Mohd Ghazali;Saranraj Karuppuswami;Amanpreet Kaur;Premjeet Chahal;
Pages: 982 - 989
Abstract: This paper presents the fabrication and characterization of radio frequency (RF) and microwave passive structures on an air substrate using additive manufacturing (3-D printing). The air substrate is realized by 3-D printing RF structures in two separate pieces and snapped together face to face using a LEGO-like process. Spacers printed on the periphery provide the desired air substrate thickness. Metal patterning on nonplanar printed plastic structures is carried out using a damascene-like process. Various RF structures such as low dispersion transmission line, T-line resonator, high-gain patch antenna, slot antenna, and cavity resonator are demonstrated using this process. Good performance is achieved; for example, measured 50-Ω transmission line shows low loss of 0.17 dB/cm at 4 GHz, and a patch antenna (center frequency of 4.5 GHz) shows gain and bandwidth of 7.6 dB and 0.2 GHz, respectively. Details of both measured and simulation results are presented.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Accurate and Efficient Self-Calibration Algorithm of Broadband On-Wafer
Scattering-Parameter Measurements for Production Test Applications Up to
110 GHz
• Authors: Chien-Chang Huang;
Pages: 990 - 998
Abstract: This paper presents an accurate and efficient on-wafer calibration algorithm of broadband scattering-parameter measurements for radio-frequency integrated circuit production test applications. Three on-chip calibration standards with the same probe positions as those of the devices under test (DUTs) were designed to take advantage of fixed probe heads in the x-y directions during calibration and measurements. In addition, three on-chip standards-a series resistor and a shunt resistor (both of which have an offset line segment) as well as a transmission line (TL)-do not have to be characterized in advance, and the measurement reference impedance can be acquired further though self-calibration without an impedance-standard substrate (ISS). Simulation studies and experimental confirmation were conducted on GaAs substrates, from 2 to 110 GHz, in addition to comparisons of the multiline thru-reflect-line (TRL) calibration results.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• Introducing IEEE Collabratec
• Pages: 999 - 999
Abstract: IEEE Collabratec is a new, integrated online community where IEEE members, researchers, authors, and technology professionals with similar fields of interest can network and collaborate, as well as create and manage content. Featuring a suite of powerful online networking and collaboration tools, IEEE Collabratec allows you to connect according to geographic location, technical interests, or career pursuits. You can also create and share a professional identity that showcases key accomplishments and participate in groups focused around mutual interests, actively learning from and contributing to knowledgeable communities. All in one place! Learn about IEEE Collabratec at ieeecollabratec.org.
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

• IEEE Open Access Publishing
• Pages: 1000 - 1000
PubDate: June 2017
Issue No: Vol. 7, No. 6 (2017)

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