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Publisher: Springer-Verlag   (Total: 2335 journals)

 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [5 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2335 journals]
• Improving HRR in 3P–8P harmonic rejection mixer using modified input
transconductance stage in hard switching mixer
• Authors: Maran Ponnambalam; Mythily Kanaga; Premanand Venkatesh Chandramani
Pages: 1 - 7
Abstract: This Paper focuses on improving the Harmonic Rejection Ratio (HRR) and the linearity of 3-Path 8-Phase harmonic rejection mixer with modified transconductance stage. The mixer core incorporates a feed-forward compensation technique in the transconductance stage for improving the linearity of the mixer with an Third order Input Intercept Point (IIP3) of 14 dBm. The Harmonic Rejection Mixer (HRM) using mixer cores with modified transconductance stage was designed using 90 nm CMOS process technology and the simulation results shows an improvement of IIP3 point of more than 25 dBm. A conversion gain of 12–4 dB was observed over the frequency range of 2.26–2.8 GHz (540 MHz bandwidth). Maximum third order HRR ( $$HRR_3$$ ) of 45 dB and fifth order HRR ( $$HRR_5$$ ) of 55 dB was observed on sweeping the RF power from −30 to 10 dBm. Deviations on the performance of the HRM was found to be very minimal on PVT variation.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0947-x
Issue No: Vol. 91, No. 1 (2017)

• An ultra-wideband pico-second true-time-delay circuit with differential
tunable active inductor
• Authors: Yang Chen; Wenyuan Li
Pages: 9 - 19
Abstract: An ultra-wideband (UWB) active true time-delay circuit with a differential tunable active inductor for LC-tank is presented and fabricated in a 0.18 μm CMOS process. The proposed delay circuit consists of a transistor, a differential active inductor (DAI), a resistor and a load, which can be approximated by a second-order all-pass filter as the basic delay element to improve the delay resolution in UWB beam-forming timed array and also be used as the hardware delay to enhance the handling speed in high-speed parallel signal processing. A novel DAI using the g m-boosting and the negative impedance transformation techniques is designed to improve delay precision and bandwidth. The proposed active delay circuit is realized without any passive inductors, which can reduce the chip area and fabricated cost. Within 3–12 GHz, the measured group delay is tunable from 6 to 8.5 ps with <10% variation and gain fluctuation is kept within 0.5 dB. The chip experimentally demonstrates an input 1-dB compression point of 14.6 dBm and consumes 12 mW from a 1.8-V supply. The core area is only 85 μm × 45 μm due to the absence of the spiral inductor. To the authors’ best knowledge, this work is firstly published that the second-order allpass filter using active inductor has the picosecond-delay time in silicon-based GHz frequency range.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0927-1
Issue No: Vol. 91, No. 1 (2017)

• Novel inspection-based mid-band derivations for CMOS cascodes and g m
-boosted topologies along-with simplified compound structure gain-analysis

• Authors: S. M. Rezaul Hasan
Pages: 21 - 41
Abstract: This article demonstrates simplified mid-band derivations for CMOS cascode and g m-boosted cascode. While the cascode mid-band analysis is addressed in some textbooks through varying brief treatments, it is provided in this paper in a more in-depth and consolidated form using an easy approach. The detailed analysis of g m-boosted cascode stage is mostly not available in textbooks (or any Web source) despite being an important analog building block in achieving gain enhancements. The mid-band analysis of this stage is made easy in this paper using a simple short circuit and inspection technique. There is no need to write or solve lengthy equations. Transformation of dependent current sources through “opportunistic short circuits” is utilized often in achieving this ease in derivation. An interesting new concept of “Algebraic ground” or “Meta-ground” is introduced in relation to the g m-boosted cascode. Some novel compound cascode stages with simplified approach to their mid-band derivations is also provided. Additional insight is also provided through a comparison of the cascode with the g m-boosted cascode using the simplified models and derivations which is rarely available elsewhere.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0881-3
Issue No: Vol. 91, No. 1 (2017)

• A novel CMOS G $$_{m}$$ m -C complex filter design for multi-mode multi
band wireless receiver applications
• Authors: Chintala Yehoshuva; B. Naresh Kumar Reddy; Venkata Reddy Ambati; Suresh Kumar Pittala
Pages: 43 - 51
Abstract: This paper presents a new approach of $$G_m$$ C complex filter for multi standard wireless receiver applications. In order to get high IRR with low power consumption a novel architecture of $$G_m$$ C complex filter has been proposed with the combination of first order left shifting and right shifting notch filters. The filter is designed in 180 nm CMOS technology and it has a power consumption of 580 μW from 1.8 V supply voltage. This novel approach can be used for multiband multi standard wireless receiver applications, because this filter can be tuned to operate in different frequency bands with different centre frequencies like bluetooth, UMTS, WLAN, GPS etc. In this paper the complex filter for bluetooth applications with a bandwidth of 2 MHz has designed and results are compared with the previous filter topology. The proposed filter achieves around 51 dB image rejection ratio at the center frequency of 4 MHz with using just a third order filter. The power consumed by the proposed filter is 52 $$\,\%$$ less than the existing topology.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0823-0
Issue No: Vol. 91, No. 1 (2017)

• A 0.7-V, 8.9- $$\upmu \hbox {A}$$ μ A compact temperature-compensated
CMOS subthreshold voltage reference with high reliability
• Authors: Sen Huang; Shengxi Diao; Fujiang Lin
Pages: 53 - 61
Abstract: This paper focuses on the study of a compact tem-perature-compensated CMOS voltage reference (VR) with high reliability. The temperature coefficient (TC) of the gate-source voltage for a subthreshold NMOSFET has been derived and utilized to perform effective temperature compensation with a proportional to absolute temperature (PTAT) drain current. The desirable PTAT current is provided with reliable power supply rejection ratio (PSRR) based on low-voltage self-biased cascode subthrehold operation with enhanced negative feedback. The resulting reference voltage is less sensitive to the process variations of on-chip resistors and absolute currents as well as the TC and PSRR. In addition, the impact of the gate-source voltage variation is alleviated, thus ensuring high reliability of the proposed VR. The measurement results without trimming in 40-nm CMOS process demonstrate that the average of TC is 5.1 and 19.1  $$\hbox {ppm}/^\circ \hbox {C}$$ in the temperature range of −20 to −80  $$^\circ \hbox {C}$$ and −40 to −120  $$^\circ \hbox {C}$$ , respectively, and the worst PSRR of −55.0 dB at 300 kHz is achieved, while the line regulation is better than 0.32 mV/V in the supply range of 0.9–1.6 V. The average current consumption is 8.9 $$\upmu \hbox {A}$$ at 0.7-V supply, with a die area of only 0.006  $$\hbox {mm}^2$$ .
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0928-0
Issue No: Vol. 91, No. 1 (2017)

• Systematic design and implementation of a high-robust adaptive calibration
technique for ETI-induced analog front end circuits in EEG systems
• Authors: Jingyi Song; Yikai Wang
Pages: 63 - 72
Abstract: Robustness is a major concern of wearable electroencephalogram (EEG) acquisition systems. It is often closely tied with variations of electrode to tissue interface (ETI), resulting in significant difficulties for following analog front end (AFE) circuitry design and signal processing. To realize a high-robust EEG system and relax the AFE requirements, adaptive ETI characterization and signal calibration techniques are proposed. Instead of monitoring ETI impedance and/or employing an active electrode, this paper demonstrates an attempt to continuously detect dc offset and ac-coupled gain variations of an entire ETI-induced signal acquisition path (ETI-AP). Both additional and multiplicative factors of distorted signals are stabilized by an adaptive coefficient compensation algorithm, which modulates the non-stationary ETI-AP to a constant channel. During EEG measurement, a pseudo-random number sequence generated from a FPGA is driven to body as a test signal to estimate and compensate the ETI-AP characteristic. The proposed techniques were evaluated in lab environments where both spontaneous and evoked EEGs were recorded by using a bipolar montage on a long-haired, healthy adult. Furthermore, foam-covered and pin-based electrodes were placed on the participant’s scalp and skin surface in order to establish different ETI conditions. With this proposed technique, the empirical results shown the dynamic variation of non-stationary ETI was continuously characterized; calibrated EEGs achieved higher signal to noise ratio, which demonstrates the validity of the proposed method, as well as its compatibility with diverse sensors and bio-medical acquisition systems.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0925-3
Issue No: Vol. 91, No. 1 (2017)

• An in-probe low-noise low-power variable-gain receive amplifier for
medical ultrasound imaging using CMUT transducers
• Authors: Hourieh Attarzadeh; Trond Ytterdal
Pages: 73 - 81
Abstract: In this paper a low-power, low-noise receiver amplifier is designed for interface with capacitive micro-machined ultrasonic transducers (CMUT). In 3D in-probe ultrasound imaging systems, the interface circuit area constraint due to the specified area per CMUT element, and the circuit power constraint for each channel are the main design challenges. A fully-differential variable-gain transimpedance amplifier (VGTIA) is designed for the CMUT signal read-out. Due to the small area and low power consumption, the circuit is suitable for in-probe imaging. The VGTIA is designed for the interface with an ADC block that does the digital conversion inside the probe. The circuit is able to produce a differential output from a Zero-Bias CMUT, where the requirement for an external high voltage dc bias is eliminated. The amplifier is designed and fabricated using a 65 nm CMOS process technology. The measurement results show that the transimpedance amplifier has a gain range of 79–97 dB $$\Omega$$ . A noise figure (NF) of 3 dB at a 5 MHz center frequency with an only 180  $$\upmu$$ W power consumption is measured. A total area of 76 $$\,\upmu$$ m $$\times$$ 50 $$\,\upmu$$ m is achieved which relaxes the area requirement for the following ADC block.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0922-6
Issue No: Vol. 91, No. 1 (2017)

• Short critical area model and extraction algorithm based on defect
characteristics in integrated circuits
• Authors: Jun-Ping Wang; Yao Wu; Teng-Wei Zhao
Pages: 83 - 91
Abstract: In the process of nano-electronic circuit design, there are defects inevitably. Due to the variety of defects and nets on circuits, the extraction of the critical area leading to the short circuit fault has become the bottleneck of layout optimization and of integrated circuit yield estimation. This paper proposes a new model of short critical area and extraction algorithm based on short circuit faults caused by redundant defects, combining the redundant defect features and mathematical morphology theory. Firstly, defect feature sizes and the nets ranges of the circuit are extracted. Secondly, according to the definition of short critical area and utilizing the expansion operation of mathematical morphology a new model of short critical area of regular nets is derived. Finally, extraction algorithm of short critical area is designed and implemented in accordance with the new model. The new model and extraction algorithm have the characteristics of being more generic and being independent of the shape features of defects and nets. Compared with the existing models, the new model has the similar performance however the extraction algorithm has significantly raised time efficiency. Furthermore, the extraction algorithm is more efficient than the previous algorithm which is based on mathematical morphology and non-model method. The experimental results on the real layouts of synthesized OpenSparc circuit and MUSB L70 show that the proposed method is accurate and effective.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0841-y
Issue No: Vol. 91, No. 1 (2017)

• 99.2% energy saving and high-linearity switching method for SAR ADCs
• Authors: Jin Zhang; Ruixue Ding; Zhangming Zhu
Pages: 93 - 96
Abstract: A high energy saving and high linearity switching method of successive approximation register analogue-to-digital converters is presented. Based on the third reference voltage V cm and split-MSB switching procedure, the proposed switching scheme achieves 99.2% less switching energy and 75% less number of capacitors over the conventional architecture. Moreover, the proposed scheme also achieves DNL and INL only 0.117LSB and 0.144LSB, respectively.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0895-x
Issue No: Vol. 91, No. 1 (2017)

• A CMOS differential receiver dedicated to nuclear magnetic resonance
applications
• Authors: Hossein Pourmodheji; Ebrahim Ghafar-Zadeh; Sebastian Magierowski
Pages: 97 - 109
Abstract: This paper examines the design and implementation of a 21 MHz CMOS differential or so-called dual-path receiver (DPR) dedicated to nuclear magnetic resonance (NMR) spectrometer. This receiver features a CMOS chip incorporated with two mini-Coils and other circuitries. Herein we discuss the design and implementation of the DPR chip as the core part of this new NMR system. The DPR consists of two differential low-noise amplifiers, voltage buffers, phase shifters and variable gain amplifiers in order to accurately cancel the effect of the background NMR signal. We put forward the design and analysis of the DPR chip and thereafter demonstrate and discuss the simulation and experimental results. Based on these results, the front-end receiver achieves a voltage gain of 80 dB at a low input referred noise of 2.7 nV/√Hz. The chip is designed in a 0.13-µm CMOS technology and occupies an area of 1 mm × 2 mm. As per experimental results, this device can be used n the future low-cost NMR technologies.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0901-3
Issue No: Vol. 91, No. 1 (2017)

• Single BJT based temperature measurement circuit without MIMC and
calibration
• Authors: Jan Ledvina; Ivan Koudar; Pavel Horský
Pages: 111 - 118
Abstract: This paper presents a temperature measurement circuit which uses only one single Bipolar Junction Transistor for ∆Vbe measurement. This type of measurement is suitable for Complementary Metal–Oxide–Semiconductor (CMOS) processes, where characterized Thermal Sensing Diodes (TSDs) are available. Measurements are based on dynamic biasing which is synchronized with Correlated Double Sampling to suppress 1/f noise, offset and reduce power consumption in the sensor. Furthermore, this work avoids the use of Metal Insulator Metal Capacitors, which might be a cost concern for some designs. Based on these criteria, a test chip was designed and manufactured in standard 110 nm CMOS technology. Without any trimming, an accuracy of ±7.3 °C (3σ) over a temperature range of −40 to 125 °C was achieved. Measurements were performed across one typical wafer and 4 process corner wafers. A single TSD is used as the thermal sensing element. The circuit occupies an area of 0.26 mm2 and has an energy consumption of 1.3 uJ per conversion.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0911-1
Issue No: Vol. 91, No. 1 (2017)

• Modeling, simulation and implementation of circuit elements in an
open-source tool set on the FPAA
• Authors: Aishwarya Natarajan; Jennifer Hasler
Pages: 119 - 130
Abstract: An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0914-y
Issue No: Vol. 91, No. 1 (2017)

• Design of new practical phase shaping circuit using optimal pole–zero
interlacing algorithm for fractional order PID controller
• Authors: Mohan V. Aware; Anjali S. Junghare; Swapnil W. Khubalkar; Ashwin Dhabale; Shantanu Das; Rutuja Dive
Pages: 131 - 145
Abstract: This paper presents the implementation of fractional order PID (FO-PID) controller using hardwired modules of constant phase element (CPE). A new approach of phase shaping by slope cancellation of asymptotic phase plots for zeros and poles within the given bandwidth is realized. Analog circuits, which exhibit analog fractional-order integrator and fractional-order differentiator, are used for building the FO-PID controller. The design procedure is developed to obtain the optimal pole–zero pairs and respective “Fractance” components to realize for any value of fractional differ-integrator. These CPE elements give minimum error tolerance over the set phase value by using commercially available (R–C) components and Op-Amps. The pole–zero location in the root locus plot with constant asymptotic angle under various feed-forward gains is achieved with these analog integrodifferential circuits of the FO-PID. The iso-damping feature of the controller is practically demonstrated. A comparative performance is demonstrated under various settings of feed forward gains, which indicate the constant overshoot with FO-PID against the conventional PID. These circuits are developed and implemented with a DC motor emulator to confirm the designed performance of the controller.
PubDate: 2017-04-01
DOI: 10.1007/s10470-016-0920-0
Issue No: Vol. 91, No. 1 (2017)

• Erratum to: Design of new practical phase shaping circuit using optimal
pole–zero interlacing algorithm for fractional order PID controller
• Authors: Mohan V. Aware; Anjali S. Junghare; Swapnil W. Khubalkar; Ashwin Dhabale; Shantanu Das; Rutuja Dive
Pages: 147 - 148
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0946-y
Issue No: Vol. 91, No. 1 (2017)

• A novel switching scheme and area-saving architecture for SAR ADC
• Authors: Ruixue Ding; Hongzhi Liang; Shubin Liu
Pages: 149 - 154
Abstract: A novel area-saving architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analogue-to-digital converters is proposed. In the proposed architecture, the higher voltage potential side of the capacitor array removes the most-significant bit (MSB) capacitor. Furthermore the proposed technique achieves 81.25% reduction in capacitor area over the conventional SAR. Based on the third reference voltage V CM and split-MSB switching procedure, the proposed switching scheme achieves 98.53% less switching energy over the conventional architecture, while no reset power dissipation. Besides the significant energy saving, this asymmetric capacitor architecture also has a well performance in linearity simulation. Resulting from the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.152LSB and 0.115LSB, respectively.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0924-4
Issue No: Vol. 91, No. 1 (2017)

• Wideband and multiband long-term evolution transmitter using envelope
delta-sigma modulation technique
• Authors: Young-Kyun Cho; Bong Hyuk Park; Choul-Young Kim
Pages: 155 - 162
Abstract: This letter presents a fully integrated tri-state radio frequency (RF) modulator for wideband and multiband long-term evolution (LTE) transmitters. The quantization noise was effectively reduced by using an envelope modulator equipped with a single-opamp resonator, thereby improving the wideband efficiency and linearity. Broadband design techniques with RF building blocks enable multiband operation. A power amplifier with dual mode supply was designed to confirm the effectiveness of the proposed scheme. The RF modulator was implemented in a 130 nm CMOS process with an active area of 3.4 mm2. At carrier frequencies from 960 MHz to 3 GHz for a 20-MHz LTE signal, the measured coding efficiency, adjacent channel leakage ratio, and error vector magnitude were found to exceed 71%, −36 dBc, and 3.9%, respectively.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0926-2
Issue No: Vol. 91, No. 1 (2017)

• Capacitive cancellation technique in design of CMOS low noise amplifier
for ultrasound applications
• Authors: Yarallah Koolivand; Omid Shoaei; Shahin Jafarabadi-Ashtiani
Pages: 163 - 169
Abstract: In this paper active capacitive cancellation technique, is proposed for alleviating the side effects of the parasitic capacitance of the ultrasound piezoelectric probe and cable. This parasitic capacitance imposes a low frequency pole at the input of the circuit, which deteriorates the noise and the transient response of the circuit, crucial parameters for ultrasound imaging systems. Employing a capacitor in a positive feedback loop of a well-defined gain amplifier actively cancels the parasitic capacitance at the input of the amplifier. Making use a binary weighted capacitor bank keeps the circuit safely away from the instability problems due to the variations of process and corner cases. For verification of the proposed technique, the circuit was designed and simulated in a 0.18 µm, 1.8 V CMOS technology. Simulation results show that this technique for equal power consumption presents a better noise performance and more than 100% higher bandwidth compared to the conventional active resistive termination approach.
PubDate: 2017-04-01
DOI: 10.1007/s10470-017-0936-0
Issue No: Vol. 91, No. 1 (2017)

• Improved double noise coupling ΔΣ analog-to-digital converter
• Authors: Youngho Jung; Gabor C. Temes
Abstract: In Jung et al. (Electron Lett 48(10):557–558, 1), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference, 2). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.
PubDate: 2017-03-16
DOI: 10.1007/s10470-017-0955-x

• A new switched current circuit fault diagnosis approach based on
pseudorandom test and preprocess by using entropy and Haar wavelet
transform
• Authors: Ying Long; Yuejun Xiong; Yigang He; Zhen Zhang
Abstract: This paper presents a new switched current (SI) circuit fault diagnosis approach based on pseudorandom test and preprocess by using entropy and Haar wavelet transform. The proposed method has the capability to detect and identify faulty transistors in SI circuit by analyzing its time response. The use of pseudorandom sequences as a stimulate signal to SI circuit reduces the cost of testing and the overhead of the test generation circuit, and using entropy and Haar wavelet transform to preprocess the time response for feature extraction drastically improves the fault diagnosis efficiency. For both actual experiment and analysis of switched current filters in Z transform (ASIZ) simulation, a low-pass, a band-pass SI filter and a clock feed-through cancellation circuit have been used as test examples to verify the effectiveness of the proposed method. The result shows that the accuracy of fault recognition achieved is about 100% by analyzing low-frequency approximations entropy and high-frequency details entropy. Therefore, it indicates that the presented method is superior than other methods.
PubDate: 2017-03-11
DOI: 10.1007/s10470-017-0950-2

• A 0.6 V and 0.395 pJ/bit nonius TDC for a passive RFID pressure
sensor tag
• Authors: Ainara Jimenez; Andoni Beriain; Juan Francisco Sevillano; Ivan Rebollo; Roc Berenguer
Abstract: This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 μs. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.
PubDate: 2017-03-10
DOI: 10.1007/s10470-017-0954-y

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