Abstract: A 12bit 250MSPS pipeline analog-to-digital converter (ADC) with serial output interface is presented. The pseudo random digital calibration dithered sub-ADC in first stage is used to lower non-ideal errors and improve the dynamic performance in the high speed ADC. An integrated serial output interface is implemented to convert 12bit parallel data into a differential serial data stream. The pipeline ADC was fabricated with CMOS 180 nm 1.8 V 1P5 M process. The active ADC with the serial output interface consumes a power consumption of 395 mW and occupies an area of 8.0 mm2, where the active area of the interface is 0.75 mm2. The measurement results show that the differential non-linearity and integral non-linearity of the proposed ADC are − 0.22/+ 0.16LSB and − 0.4/+ 0.6LSB, respectively. The spurious free dynamic range and signal-to-noise ratio can get 81.17 dB and 69.92 dB with 20 MHz input signal at full sampling speed. The serial output interface provides an eye height greater than 800 mV for data rates of 4 GHz bits per second with a power of 75 mW. PubDate: 2019-01-19

Authors:Jisu Elsa Jacob; Gopakumar Kuttappan Nair; Ajith Cherian; Thomas Iype Abstract: In this study, we have investigated whether fractal dimension is a useful non linear feature for distinguishing electroencephalogram (EEG) of cases with encephalopathy from that of normal healthy EEGs. Both Higuchi’s fractal dimension and Katz’s fractal dimension were computed and were statistically analyzed between the normal and disease groups. Both parameters showed significant difference between the normal and encephalopathy groups, though Higuchi’s fractal dimension showed better discriminating ability. Support Vector Machine (SVM) classifier was also applied for the automated diagnosis of encephalopathy based on EEG. It has been found that SVM classifier performed better when Higuchi’s fractal dimension was utilized as feature set than using both Higuchi’s and Katz’s FD together. PubDate: 2019-01-13 DOI: 10.1007/s10470-019-01388-z

Authors:Menglian Zhao; Yanxia Yao; Haozhou Zhang; Xiaobo Wu Abstract: This paper introduces a ripple-based adaptive on-time controlled buck converter with pseudo triangular ramp compensation. Ripple-based control has its advantages over traditional PWM control of fast response and simple structure without frequency compensation network. Constant on-time (COT) control is one of the conventional ripple-based control methods, which needs large output capacitance with large ESR to guarantee the system stability, yet leading to large output ripple. In order to strengthen system stability with small output ripple and fast transient response, a novel pseudo triangular ramp compensation is proposed. Also COT control has its drawback of switching frequency variation. Therefore an adaptive on-time generator is adopted to fix switching frequency, in which VO/N2RS and Vin/N2RS are used as current sources to eliminate the effect of input/output voltage. A voltage outer loop is also adopted to improve DC precision. The power MOSFETs are integrated inside the chip. The proposed converter was implemented in 0.18 μm 5 V CMOS process. Experimental results show that the output ripple is around 20 mV. The switching frequency can be fixed at 2.5 MHz with only 1% variation. Also with 330 nH off-chip power inductor, this converter can output up to 6 A load current. Measured peak efficiency is 85%. PubDate: 2019-01-12 DOI: 10.1007/s10470-019-01390-5

Authors:Milad Ekhteraei; Mohsen Hayati; Farzin Shama Abstract: This Paper presents a microstrip lowpass filter (LPF) with compact size, and ultra-wide stopband. The structure consists of a semi-circular shaped resonator (SCSR) and circular patches as the suppressing cell. The proposed LPF has a − 3 dB cutoff frequency at 1.53 GHz. It also has suitable performances such as an extended stopband width from 1.62 to 19.1 GHz (with the attenuation level of more than − 20 dB), ultra-sharp transition-band of 0.09 GHz (from − 3 to − 20 dB). Low insertion loss, high return loss and flat group delay in the region of the passband are very significant properties of this LPF. A proper agreement between the simulation and measurement results has been achieved after the fabrication and testing. Proposed LPF has an ultra-high figure-of-merit (FOM) of 126168, showing its strong efficiency. Forasmuch as harmonic control circuits (HCCs) play a key role in designing Class-F/F−1 power amplifiers (PAs); the asymmetric high performance LPFs can be used at the input and output of these PAs in the HCC section. Therefore, the proposed LPF can be suggested for this application. PubDate: 2019-01-11 DOI: 10.1007/s10470-018-01387-6

Authors:Kashif Ali Abro; Ali Asghar Memon; Anwar Ahmed Memon Abstract: The article “Functionality of circuit via modern fractional differentiations”, written by Kashif Ali Abro, Ali Asghar Memon and Anwar Ahmed Memon, was originally published electronically on the publisher’s internet portal (currently SpringerLink) on November 2018 with open access. PubDate: 2019-01-10 DOI: 10.1007/s10470-018-01385-8

Authors:Fadia Zouad; Karim Kemih; Hamid Hamiche Abstract: In this paper, a new approach to secure in perturbed receiver based on the Chen fractional order delayed chaotic system is developed and the electronics circuit is simulated with Multisim. The main idea of this approach is the injection of the transmitted message in the dynamics of the Chen fractional order delayed chaotic system in the transmitter. To recover the message from the perturbed receiver, we use the H-infinity to establish the synchronization between the transmitter and the receiver and to recover the transmitted signal. Little paper in the literature presents the electronic circuit of the secure communication using fractional order delayed chaotic system due to the difficulty of realization, for it, the electronic circuit is detailed using Multisim software to demonstrate the feasibility of the proposed approach. PubDate: 2019-01-05 DOI: 10.1007/s10470-018-01382-x

Authors:Zine Ghemari; Salah Saad Abstract: Vibration analysis is a conditional preventive maintenance technique that measures the level of vibratory motion by a measuring chain containing a vibration sensor, an amplifier and an FFT analyzer. In the present work, the vibratory analysis technique is improved on the basis of vibration sensor (capacitive sensor) developments. A suitable capacitive sensor mathematical model is developed thus; a formula of its mechanical sensitivity according to the capacitance is extracted. Experimental and simulation tests are conducted to validate the developed model. A damping rate equal to 0.68 is chosen to reduce the measurement error to a value not exceeding 0.5% in order to increase the accuracy to a value greater than or equal to 99.5%, consequently the sensor mechanical sensitivity is optimized. Finally, the simulation of the developed model is carried out for two capacitive sensors. The first sensor is used in the experimental tests and has a damping rate equal to 0.64 and the second is the sensor proposed in this work, having a damping rate equal to 0.68. The comparison of the obtained results has showed that the damping rate of 0.68 has greatly improved the capacitive sensor performances. PubDate: 2019-01-05 DOI: 10.1007/s10470-018-01383-w

Authors:Arpita Ghosh; Amit Jain; Subir Kumar Sarkar Abstract: This work represents the implementation of a data transfer system using single electron threshold logic based approach. The power consumption of the complete system is 239.2 pW. The complete implementation of the design along with the simulation results of different individual stages is presented in this work. The reliability of the system is one of the main concerns as the background charge fluctuation affects the overall system performance. Considering the background charge to be uniformly and normally distributed the variation of the percentage of reliability along with the variation factor for different type of distributions has been plotted and explained. The stability issue of the circuit has also been discussed using stability plots. PubDate: 2019-01-05 DOI: 10.1007/s10470-018-01384-9

Authors:Mohammad Azimi Dastgerdi; Mehdi Habibi; Mehdi Dolatshahi Abstract: Sensor network architectures have gained significant attention in acquiring data over widespread areas. To avoid wiring and power complexities, self-powered operation is desirable in these sensors. For this purpose, low voltage and low power characteristics of the internal electronic building blocks is of significant importance. Since sensor architectures usually require voltage reference circuitry, in this paper, a low voltage, low power bandgap reference circuit block is presented. Using a new two stage topology, the line sensitivity is reduced to a significantly low value of 0.28%/V over a wider power supply range of 0.2 V to 2 V. Due to the use of MOSFETs in the subthreshold region, low voltage and low power operation of about 41 pW at 0.2 V is obtained. Furthermore by introducing a novel cross coupled architecture, the temperature coefficient is enhanced considerably. An average temperature coefficient of 247 ppm/°C is obtained at different corners. The performance of the architecture is studied in a 0.18 µm process using post layout and Monte Carlo evaluations. The evaluation results show improvements in both line sensitivity and temperature coefficients compared with previous work. PubDate: 2019-01-03 DOI: 10.1007/s10470-018-1379-y

Authors:Mahdiar Azizi Poor; Omid Esmaeeli; Samad Sheikhaei Abstract: In this article, a low phase noise quadrature VCO (QVCO) is proposed, which uses superharmonic injection and current reuse techniques to reduce phase-noise and power consumption. The LC tank circuit quality factor is improved, using a negative resistance. PMOS transistors have also been used instead of NMOS transistors. As a result of these modifications, further phase noise reduction is achieved. The QVCO consists of a VCO operating at 2ω0 (twice the operating frequency) injecting its output signal into the common source nodes of two other oscillators operating at ω0. Using this superharmonic injection technique, in addition to phase noise reduction, the chance of injection pulling caused by powerful PA signals is reduced. Also, the current reuse technique automatically adapts its voltage to the requirement of the supplied stages, therefore, it is not limiting the VCO output swing. Designed for the 900 MHz band and simulated in a 0.18 µm CMOS technology with 1.8 V power supply, the circuit achieves a phase noise of − 141.5 dBc/Hz at 1 MHz offset frequency, while consuming 12.8 mW power. The proposed circuit is compared with several re-simulated previously published work. The comparison shows 17.5 dB reduction in phase noise compared to conventional P-QVCO, while consuming the same amount of power. PubDate: 2019-01-02 DOI: 10.1007/s10470-018-1380-5

Abstract: The penetration of gamma in neutron spectra reduces the accuracy of measurement results, especially when using the scintillation detector. The digital method can be used to identify either neutron or gamma pulses. In order to select the algorithm for detector using EJ-301 liquid scintillator (EJ-301 detector), the Matlab Simulink tool was used to simulate neutron counting system. The results show that the figure of merits (FoM) of threshold crossing time (TCT), pulsed gradient analysis (PGA), charge comparison (CC), and correlation pattern recognition (CPR) methods for the energy threshold 50 keVee (keV electron equivalent) are 1.1, 0.84, 2.34 and 1.04, respectively. An experiment was conducted with prototype EJ-301 detector and the DRS4 digitizer to validate simulation results. PubDate: 2019-01-01

Abstract: A voltage-controlled current source in 0.35 μm BiCMOS technology is presented. A linear relationship between the control voltage and the output current is achieved by using first generation current conveyors in configuration of simple voltage-to-current converters. The control voltages of the DC and the AC output currents are completely independent of each other. The current source is intended for the generation of small currents in a sub-microampere range and in a frequency range of a few hundreds of megahertz. The measured and simulated results confirm that the smallest amplitudes of the generated currents are down to 100 nA, with a single supply voltage of 1.3 V. The small-signal bandwidth ranges from 15 up to 900 MHz. PubDate: 2019-01-01

Abstract: This paper addresses the problem of speech quality enhancement by adaptive two-channel filtering algorithms. Recently, the forward blind source separation structure has been proposed and combined with normalized least-mean-square algorithm (FNLMS). The main drawback of two-channel FNLMS algorithm is its poor performance in steady state regime when the fixed step-sizes values are selected large. However, the slow convergence rate is observed with the small fixed step-size values. In this paper, we propose three new combinations of the basic FNLMS algorithm with simple variable step-sizes approaches, for improving both the steady state values and convergence rate (noted TVSF for Two-channel Variable Step-size Forward). In these modifications, we propose new configuration of two-channel forward structure by three simple and efficient variable step-sizes estimations. To confirm the good performance of three proposed TVSF algorithms compared with the classical fixed-step-size version, we have carried out several simulations in very noisy situations using several criteria. PubDate: 2019-01-01

Abstract: This paper presents the implementation of symmetric folded meandered-line structure that includes a quad-section stepped impedance resonator (QSIR). The existence of four stop bands at 1.81/5.16/8.08/10.90 GHz was successfully synthesized by the incorporation of QSIR comprising an electrical length of 0.84λg–0.19λg–0.15λg–0.22λg. The throughput of the filter was further improved by the inclusion of five attenuation poles at 340 MHz, 3.24, 6.38, 9.45, and 11.92 GHz with the rejection levels of − 32.19, − 25.19, − 28.68, − 21.57, − 32.63 dB, respectively. The concept achieves a wide fractional bandwidth of 59/18.23/13.86/10.46% at 1.81/5.16/8.08/10.90 GHz, respectively. Noticeable attenuation of − 25 dB at the respective stop bands in the frequency range of 2.34–1.28, 5.60–4.66, 8.56–7.44, and 11.35–10.21 GHz, with a spurious-free response up to 13 GHz was confirmed. Furthermore, a sharp response is demonstrated by a simulation and shows strong agreement with the measurement results. PubDate: 2019-01-01

Abstract: A novel square root circuit using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. FGMOS transistors are being utilized in a number of new and exciting analog applications. These devices are available in standard CMOS technology because they are being widely used in digital circuits. FGMOS structures are also known as multi-input MOS and their multi input advantages make it simpler to realize an arithmetic signal processing circuit. Thus floating gate devices are now finding wider applications by analog researchers. The FGMOS drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only four FGMOS transistors in proposed square-root circuit. The main feature of this remarkably simple square root circuit is to reduce the errors generated by the second order effects in the current mode circuits employing translinear loop. PubDate: 2019-01-01

Abstract: A third-order quadrature sinusoidal oscillator (TOQSO) is proposed employing two voltage differencing inverting buffered amplifiers (VDIBAs), three grounded capacitors and a resistor. The proposed TOQSO enjoys electronically tunable, non-interactive condition and frequency control. The TOQSO uses all grounded capacitors, which is suitable for IC implementation. Moreover, the internal CMOS realization of VDIBA is possibly the simplest among all recently introduced new active building blocks. SPICE simulation results have been provided to support the validity of proposed TOQSO using TSMC 0.18 µm technology. PubDate: 2019-01-01

Abstract: This paper presents a 24–28 GHz high-stability millimeter-wave power amplifier (PA) implemented in low-cost \(0.13\, \upmu \hbox {m}\) CMOS process. The PA consists of two cascode stages with passive transformer-based input and output baluns. The common-gate-shorting technique is proposed for high-stability and high-gain millimeter-wave cascode stage. To realize this technique, an interdigited powercell structure is adopted for MOS layout optimization. In order to improve \(\hbox {P}_{out}\) and PAE, an inter-stage inductor is introduced. The proposed PA achieves a PAE over 16.3% with a saturated output power of 17.5 dBm. The maximum gain is 21.2 dB at 26 GHz. PubDate: 2019-01-01

Abstract: This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass filter based on an improved Active-gm-RC stage. Challenges related to the design of analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art. PubDate: 2019-01-01

Abstract: In this paper, a novel wideband bandpass filter using half-mode substrate integrated waveguide (HMSIW) structure loaded by complementary Z-shaped resonator (CZR) is proposed. The working principle of the proposed filter is based on the evanescent-mode propagation. The CZR unit-cell behave as a magnetic dipole, which is able to generate a backward-wave passband region below the cut-off frequency of the SIW–CZR structure. Since, the electrical size of the proposed CZR unit-cell is larger than the conventional complementary electric-LC unit-cell with the same size, therefore this unit-cell is a good candidate to miniaturize the SIW structure. As well as, the SIW filter loaded by the proposed CZR unit-cell presents a wider bandpass compared to the SIW filter loaded by the conventional resonant metamaterial unit-cells. In order to validate the ability of the proposed CZR unit-cell in size reduction and increasing bandwidth, the proposed one- and two-stage HMSIW–CZR filters have been fabricated and tested. The measured S-parameters of the fabricated filters are in a good agreement with the simulated ones. It is the first time that the CZR unit-cells were combined with the SIW structure to miniaturize the SIW structure and increase the bandwidth. The total size of the proposed two-stage filter is 0.62 λg × 0.26 λg. PubDate: 2019-01-01

Abstract: A miniaturized inter-digitated hairpin resonating BPF structure with centre frequency of 1.3 GHz suitable for GPS was designed with FR4 substrate. Ratioed CSRR DGS structures act as slow wave resonators extending the stop band of the filter. To maximise filter bandwidth selectivity and reflection coefficient and to optimize coupling coefficient, parametric study on both dimensions of hairpin structure and CSRR structures was conducted. The Inter-digitated hairpin filter with dimensions of 32 × 32 mm2 achieves 20 dB of reflection coefficient, 0.12 dB of transmission coefficient and 20 dB of harmonic suppression. PubDate: 2019-01-01