Publisher: Springer-Verlag (Total: 2570 journals)

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 Analog Integrated Circuits and Signal ProcessingJournal Prestige (SJR): 0.211 Citation Impact (citeScore): 1Number of Followers: 11      Hybrid journal (It can contain Open Access articles) ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030 Published by Springer-Verlag  [2570 journals]
• A 99.79% energy saving switching scheme without third reference level and
• Abstract: Abstract An energy-efficient capacitor switching scheme is proposed for successive approximation register analog-to-digital converter. During the design process, the semi-resting DAC structure and charge characteristic of floating capacitor ensure significant energy saving. There is no switching power consumption in the first two comparison process. Compared with the conventional switching scheme, the proposed method decreases 99.79% switching energy and 73.8% capacitor area. Benefit from merge-and-split method, only two reference levels are utilized in this novel scheme, where the power and accuracy of generating the third reference voltage are not necessary to consider. Besides, the reset energy of the proposed scheme is verified to be 0. Furthermore, the common mode voltage at comparator inputs is kept at 0.5Vref except merely a 0.5LSB reduction due to LSB-down technique.
PubDate: 2020-02-07

• A nature inspired optimization algorithm for VLSI fixed-outline
floorplanning
• Abstract: Abstract VLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named as ‘Lion Optimization Algorithm’ (LOA). LOA is developed for non-slicing floorplans having soft modules with fixed-outline constraint. Although a number of GAs are developed for solving VLSI floorplan optimization problems, they are using weighted sum approach with single objective optimization and crossover between two B*tree structure is not yet attempted. This paper explains, power of B*tree crossover operator for multiobjective floorplanning problem. This operator introduces additional perturbations in initial B*tree structure to create two new different B*tree structures compared with classical GA approach. Simulation results on Microelectronics Center of North Carolina and Gigascale Systems Research Center benchmarks indicate that LOA floorplanner achieves significant savings in wirelength and area minimization also produces better results for dead space minimization compared to previous floorplanners.
PubDate: 2020-02-05

• Multi-stage CMOS amplifier frequency compensation using a single MOSCAP
• Abstract: Abstract A multi-stage amplifier is a frequency compensated via a single and small MOSFET based capacitor. The idea reduces die occupation considerably since removes any passive elements in the compensation network. Also, a normal differential pair and a MOSFET based capacitor form compensation network and boost DC gain simultaneously. The proposed approach is symbolically described via MATLAB and numerically simulated via HSPICE circuit simulator using standard TSMC 0.18µ CMOS technology. According to mathematical justifications and simulation results, the proposed amplifier shows operation excellency especially in terms of die occupation and frequency response parameters which make it appropriate choice to realize larger analog and mixed mode systems like modulators and data converters.
PubDate: 2020-02-04

• Electronically controllable third-order quadrature sinusoidal oscillator
employing CMOS-OTAs
• Abstract: Abstract This paper describes a voltage mode third-order quadrature sinusoidal oscillator (TOQSO) based on operational transconductance amplifiers (OTAs). The proposed configuration uses three OTAs and three grounded capacitors. Outputs of two voltage mode sinusoids with 90° phase difference are found in the proposed oscillator circuit. The condition of oscillation and frequency of oscillation are independently electronically controllable by separate transconductances of the OTAs. The performance of TOQSO is tested by SPICE (version 16.5) simulation using TSMC 0.18 µm technology parameters and experimental results employing CA3080 type IC OTAs have been presented to confirm the workability of the proposed new configuration.
PubDate: 2020-02-04

• A high gain and high bandwidth three stage amplifier using FGMOS and
0.5 V dual supply
• Abstract: Abstract A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.
PubDate: 2020-02-04

• A low-jitter clock multiplier using a simple low-power ECDLL with extra
settled delays in VCDL
• Abstract: Abstract This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 μm technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.
PubDate: 2020-02-04

• A full-transistor fine-grain multilevel delay element with compact
regularity layout
• Abstract: Abstract This paper proposes a full-transistor multilevel delay element (DE) implemented by 65 nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to realize the fine-grain and coarse tuning for multilevel delay adjustment while maintain the duty cycle of input pulse. In physical design, a novel transistor array with a compact regularity layout is adopted to mitigate process variation. According to the post-layout simulation analysis, compared with two traditional delay elements, the proposed DE has particular advantages in terms of the layout area as well as achieves the acceptable merely 2× power consumption and 22.9% delay quantization error in linearity accuracy. The effective 2 MHz bandwidth and nano-second delay range is applicable to a low/medium frequency clock compensation system.
PubDate: 2020-02-03

• Precise, portable and wide band alternating current source for extremely
low current values
• Abstract: Abstract Alternating current (AC) sources which provide currents in micro ampere ranges have become essential for testing of electronic components, simulation of sensors, eddy current analysis, small signal analysis of transistors, electro-cutaneous stimulation in therapeutics, current injection in medical imaging techniques etc. This manuscript proposes a precise voltage mode AC source for extremely low current values. A simple AC source with load in the feedback is optimised experimentally by compensating the capacitive effects (approx. 4.7 pF) by employing a novel combination of general impedance converter (gic) or Negative Capacitance Converter (NCC) circuits along with basic circuit. The design is proposed with precise value of 160 $$\upmu A$$ for applications including physiological measurements. It is seen that GIC circuit modification offers better consistency and performance in load analysis compared to NCC. Load analysis (10–2000 $$\Omega$$), frequency analysis (100 Hz to 1 MHz), stability analysis and reliability testing confirm the optimised and precise operation of the proposed current source. With very high degree of matching in theoretical and practical results, calculation of output impedance is also done and the value is fair enough. The hardware incorporates direct digital synthesis chip driven by a microcontroller for generation of sine wave, thereby reducing the need of bulky power supplies and function generators. This precise alternating current source is suitable for wide band portable applications.
PubDate: 2020-02-01

• All-digital 1-1 MASH delta-sigma time-to-digital converter via time-mode
signal processing
• Abstract: Abstract This paper presents an all-digital 1-1 MASH $$\Delta \Sigma$$ time-to-digital converter (TDC) using time-mode signal processing. A cascode time adder with a raised inverter threshold voltage is proposed to minimize the deterministic timing error caused by the current mismatch of the discharge paths of the time adder. A differential time integrator consisting of a pair of identical single-ended time integrators is proposed to minimize the effect of the nonlinearities of the single-ended time integrator. The random and deterministic timing errors of the TDC are analyzed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the TDC exhibits 40 dB per decade noise-shaping at high frequencies. The cascode-configured discharge paths and raised threshold voltage of the load inverter improve the linearity of the TDC. The TDC achieves 1.9 ps time resolution over 48–415 kHz signal band while consuming 502 μW.
PubDate: 2020-02-01

• Designing programmable current-mode Gaussian and bell-shaped membership
function
• Abstract: Abstract In this paper, a procedure is proposed to implement a novel and effective Gaussian-shaped and Bell-shaped membership function. The circuit is designed in a current mode. Therefore, the power consumption has been decreased. Higher power supply rejection ratio is also achieved by the use of a differential structure. The most important aims are to design simple, accurate and low power consumption circuits. The proposed circuit operates in the saturation region. Therefore, high-accuracy, as well as the high-speed performance and independency to the temperature variations, are obtained. Programmability, power consumption and parameters variations of the proposed circuit are also presented. The simulations are done in 0.18 µm CMOS technology.
PubDate: 2020-02-01

• An up-down topology based-current mode adjustable-gain
square-rooting/geometric-mean circuit
• Abstract: Abstract A high speed low power current-mode square-rooting/geometric-mean circuit is presented in this paper. The up-down topology with MOS translinear loop in sub-threshold is the basic building block of the proposed circuit which leads to lower supply voltage requirement and body effect issues. This design is also helpful to implement the square-rooting operation of a signal and geometric-mean of two variable signals both with adjustable gain. The performance has been simulated using HSPICE software in 0.18 µm TSMC (level-49 parameters) CMOS technology. Post-layout simulation results with 1-V DC supply voltage show that the maximum linearity error of 1.3%, the − 3 dB bandwidth of 21.9 MHz and maximum power consumption of 700 nW are granted. Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the PVT (process, voltage and temperature) variations.
PubDate: 2020-02-01

• Two wide-tuning-range mm-wave VCOs with SCTL and SCCPW in 45 nm SOI
CMOS for 5G applications
• Abstract: Abstract A switched coupled transmission line (SCTL) method with high Q and flexible structure is proposed for mm-wave VCO to improve tuning range (TR), meanwhile maintaining low phase noise, low power dissipation and zero additional area. This TR extension method is also proved effective in a switched coupled coplanar waveguide (SCCPW) VCO. Fabricated in 45 nm SOI CMOS, the SCTL-VCO achieves 38.74% TR from 39.46 to 58.42 GHz, increased by 29.2% compared to the reference TL-VCO. The SCCPW-VCO achieves 38.83% TR from 38.69 to 57.33 GHz, increased by 31.9% compared to the reference CPW-VCO. The measured phase noise of SCTL-VCO and SCCPW-VCO over the entire frequency tuning range is from $$-$$ 106 to $$-$$ 116.8 and $$-$$ 106.1 to $$-$$ 116 dBc/Hz at 10 MHz offset, while the corresponding FOM$$_T$$ is from $$-$$ 181.7 to $$-$$ 192.5 and $$-$$ 181.6 to $$-$$ 191.5 dBc/Hz, respectively. Each VCO dissipates 8.6–10.8 mW from 0.7 V power supply.
PubDate: 2020-02-01

• Systematic design of CNTFET based OTA and Op amp using g m / I D technique
• Abstract: Abstract This paper presents for the first time all the steps required in optimal design of carbon nano tube field effect transistor (CNTFET) based single stage operational transconductance amplifier and two stage operational amplifier using transconductance to drain current ratio ($$g_{m}/I_{D}$$) technique for low voltage and low power applications. As square law model failed to produce exact behavior in short channel devices as well as moderate and weak inversion behavior of the transistor. Therefore, $$g_{m} / I_{D}$$ methodology is used to design analog circuits in short channel devices to overcome the shortcomings of square law models. Also, the design using $$g_{m} / I_{D}$$ methodology does not consider the inversion region of the transistor like square law equations. The $$g_{m} / I_{D}$$ methodology is a well-established technique for CMOS analog IC design but CMOS has continuous width while CNTFET width is discrete and depends on different parameters like number of tubes, pitch and diameter of the carbon nanotube. Therefore, there is a need of a design methodology to design analog circuits using CNTFETs. Circuit performance has been investigated extensively using HSPICE simulation.
PubDate: 2020-02-01

• A 4th-order 100 μA Diode-RC-based filter with 5 dBm-IIP 3 at 24 MHz
cut-off frequency
• Abstract: Abstract This paper presents a 4th-order low-pass continuous-time Diode-RC filter with 24 MHz cut-off frequency. The filter structure is based on the combination of positive (passive) and negative (using cross-coupled MOS transistors) cells to synthesize complex-conjugate-poles pairs. Moreover, the filter is designed and optimized to have high-linearity along all the filter pass-band. The filter exhibits 16 dBm-$$\text {IIP}_3$$ with 2–3 MHz input tones and 5 dBm-$$\text {IIP}_3$$ with 23–24 MHz, whereas the current consumption remains limited to $$100 \, \upmu \hbox {A}$$ from 1.8 V supply voltage.
PubDate: 2020-02-01

• Design, FPGA implementation and statistical analysis of chaos-ring based
dual entropy core true random number generator
• Abstract: Abstract In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated by uniting the chaotic system-based RNG and the RO-based RNG structures on FPGA. The chaotic oscillator structure as the basic entropy source has been implemented in VHDL using Euler numerical algorithm in 32-bit IQ-Math fixed point number standart on FPGA. The designed chaotic oscillator has been synthesized for the FPGA chip and the statistics related to chip resource consumption and clock frequencies of the units have been presented. The RO-based RNG structure has been designed as the second entropy source. Chaos-ring based dual entropy core novel TRNG unit have been created by combining of these two FPGA-based structures in the XOR function used at the post processing unit. The throughput of the designed dual entropy core TRNG unit ranges 464 Mbps. The output bit streams obtained from FPGA-based novel TRNG have been subjected to NIST 800-22 test suites.
PubDate: 2020-02-01

• Mismatch suppression and noise reduction for SAR-ADC with Bayes estimation
method
• Abstract: Abstract A statistical estimator based on Bayes Estimation theory is developed in this paper to simultaneously reduce capacitor mismatch and noise in a successive approximation register analogue-to-digital converter (SAR-ADC). Once the SAR-ADC has completed its quantization process, the residue voltage is available at the comparator input and can be estimated accurately using the Bayesian estimator. The ADC resolution is improved by subtracting the estimated residue from the digital output. The same technique of residue extraction is then used to estimate mismatches in the capacitive digital-to-analogue converter. A 15 dB improvement is observed in signal-to-noise-plus-distortion ratio by using the statistical estimator for a 10-bit SAR over a wide range of capacitance mismatch and ADC noise.
PubDate: 2020-01-22

• A fully differential capacitively-coupled high CMRR low-power chopper
amplifier for EEG dry electrodes
• Abstract: Abstract The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers’ spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 $$\upmu \hbox {W}$$ at a 1.2 $$\hbox {V}$$ supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 $$\upmu \hbox {V}_{\mathrm{rms}}$$ in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 $$\hbox {mm}^2$$ without pads.
PubDate: 2020-01-14

• A 12-bit 120-MS/s SAR ADC with improved split capacitive DAC and low-noise
dynamic comparator
• Abstract: Abstract This paper presents a 12-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with improved split capacitive DAC and low-noise dynamic comparator. A split DAC structure with parasitic capacitance depressed technique is introduced, the top-plate parasitic capacitances of MSB and LSB DAC arrays are both reduced, and the accuracy of split DAC is increased without calibration. Further, an optimized sampling method is used to provide a unit capacitance between the MSB and LSB DAC arrays, the match of DAC is improved. In addition, a high-speed dynamic comparator with input-referred noise reduction technique is proposed, an extra positive feedback loop is provided to reduce the comparison delay and the gain of the comparator is also increased to depress noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 6 mW from 1.2 V power supply with a SNDR > 66.1 dB and SFDR > 81.5 dB. The proposed ADC core occupies an active area of 0.05 mm2, and the corresponding FoM is 30 fJ/conversion-step with Nyquist frequency.
PubDate: 2020-01-09

• A 5-bit 400-MS/s time domain flash ADC in 0.18-μm CMOS
• Abstract: Abstract A 5-bit 400-MHz time-domain analog-to-digital converter (ADC) was implemented in 0.18-μm CMOS technology. The proposed design is composed of a voltage-to-time-difference converter, a flash-type time-to-digital converter, and some error correction logic. Input voltage-type signals are converted to time-difference signals by a voltage-to-time-difference converter. Its rising- and falling-edge outputs contain delay information; they can then be converted by two time-to-digital converters operating at interleaving clock phases. Because of the transparent delayed signal without a sample-and-hold circuit, the subsequent time-to-digital converter structure is of the flash type. By using a distinct RC time constant of the time comparator, the time-difference signals can be converted to the relevant 1-of-n code. Because this conversion is almost entirely digital in nature, little static current is consumed. The measured signal to noise and distortion ratio and spurious-free dynamic range of the ADC are 26.1 dB and 31.5 dB, respectively, at a 400-MHz sampling frequency for a 100-MHz input signal.
PubDate: 2020-01-07

• Compact wideband band-stop filter using stepped complementary split ring
resonators
• Abstract: Abstract The objective of this work is to achieve a compact wideband band-stop filter using complementary split ring resonators (CSRR) as the fundamental element. The relation between the geometry and resonances of the CSRR were studied analytically along with their field distribution to determine the factors governing coupling between the rings of the CSRR. The effects of the inner-outer ring orientation on resonances of the CSRR has been studied and the resulting properties have been used to design the proposed compact wideband band-stop filter prototype operating with a center frequency of 2.5 GHz and a bandwidth of 1 GHz. The area of the proposed filter is 0.078 λg2 with a fractional bandwidth of 39.76%. This structure has following advantages: more compact, wide bandwidth and occupies less area. The fabricated prototype was tested and the results were promising representing this works potential.
PubDate: 2020-01-03

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