Abstract: The performance of dc–dc power converters is critically dependent on the inductors at their core. Planar spiral inductors are compact constructions that can be scaled and integrated without the limitations of traditional wire-wound devices. Therefore, they are increasingly employed to meet the needs of modern low-power applications, especially where size, weight and manufacturing costs are deciding factors. As a planar inductor is designed to fit the parameters of an application, it is paramount to take into account the associated parasitic effects that have an impact on the converter performance. This paper analyzes how the conversion efficiency of boost and buck integrated power converters depends on the parasitics elements of planar inductors, and how it can be improved by optimizing the inductor layout. In particular, the paper provides the guidelines for maximizing the time constant of the inductor by considering the different geometrical features that define the inductor shape. The trade-offs that maximize the inductance time constant for different shapes are introduced, and an algorithm is developed to optimize the performance with no area overhead. Finally, three boost converters are designed, simulated, and compared in a 65-nm CMOS technology to demonstrate the validity of the proposed approach, and the corresponding conversion efficiency improvement is assessed. PubDate: 2019-07-08

Abstract: In this paper, an active antenna is proposed, where microwave amplifier is directly integrated on passive antenna. The amplifier provides required RF power to the antenna, hence improves the system efficiency. This paper presents a slotted patch antenna, resonating at 2.45 GHz for Industrial Scientific Medical band, having excellent return loss of − 30 dB and radiation efficiency of 100%. The microwave amplifier was designed and optimized on AWR Microwave Office software for 11 dB gain and noise figure less than 2 at the frequency of 2.45 GHz. The proposed amplifier type active antenna was designed using FR4 substrate with substrate height, 1.6 mm and dielectric constant of εr = 4.4. In active antenna, amplifier provides extra power to the antenna while electric parameters of active antenna are same, such as return loss is − 21.95 dB at 2.11 GHz and the improved bandwidth of 125 MHz. The passive antenna is designed, analyzed and optimized on IE3D Zeland software version 15.30. PubDate: 2019-07-05

Abstract: A multi-ring rotary traveling-wave oscillator (RTWO) is presented. The oscillation frequency of the main RTWO ring is designed for 42-GHz with 2-GHz tunability. Multi-phase signals generated in the main RTWO ring drive doubler circuits to generate second harmonic signals. The transformer used in each doubler circuit produces differential signals that are injected into the outer ring. Differential signals in the secondary terminals of the transformers are combined by coupled co-planar strip-line to support traveling-wave in the second ring. Bi-CMOS 0.13-µm technology is used to design and implement the multi-ring RTWO circuit. The chip area is 0.585-mm2. Total power consumption is 68-mW. SiGe HBT has been preferred over nMOS transistors to implement the gain stages, frequency doublers and the buffer circuits due to high fT and fmax of the SiGe HBTs. The measured frequency of oscillation is 42.24-GHz and 84.48-GHz with 5.6% tuning range and output power is − 20 dBm and − 45 dBm respectively. Phase noise at the main RTWO ring is − 97.5 dBc/Hz at 10 MHz. PubDate: 2019-07-03

Abstract: A flipped voltage follower structure based on a dynamic current boosting technique is proposed which enables the fast-transient behavior. It is applied to an output capacitor-less low-dropout (LDO) regulator to improve the output transient response and reduce the over/undershoots of the output voltage when the load current or the input voltage is suddenly changed. The proposed low-dropout regulator is simulated in 0.18 μm CMOS technology, which the output voltage is regulated at 1 V with a dropout voltage of about 114 mV. The output voltage over/undershoot amplitudes of the proposed LDO are obtained in 99.52/551.8 mV with the settling time of fewer than 1.3 μs for the load current changes from 0.1 to 100 mA with 200 ns rise/fall times. PubDate: 2019-07-03

Abstract: Now a days, an efficient arithmetic operations are important to accomplish the high performance. In every one of these applications, multiplier is an important arithmetic operation. Usually multipliers are utilized to evaluate the square operand. A square operation is faster than a multiplication. This paper proposes a high performance and area efficient square architecture using Anurupya Sutra of Vedic Mathematics. The proposed method is efficient method, which divided the large magnitude number into smaller magnitude numbers and concatenated smaller magnitude numbers. The proposed architecture is synthesized and simulated using Vivado design suite 2018.3 and implemented on Kintex-7 FPGA board. The results revealed a high performance and area efficient compared to a well-known prior art multipliers. PubDate: 2019-07-02

Abstract: A novel charge pump for phase locked loops application based on the self-cascode (SC) transistor is presented. The proposed charge pump is simple and adds just a few number of transistors to basic charge pump circuit. The SC transistor is self-biased and has high output impedance and lower voltage headroom. Threshold voltage reduction method is used in SC transistor to reduce transistor size, increase the output resistance and help to improve the self-biased structure. The post layout simulation for the charge pump with SC transistor is performed using 180 nm CMOS technology. Based on the Monte Carlo process variation and corner case simulation a 2% current mismatch over the voltage range of 0.35–1.48 V is observed. PubDate: 2019-07-02

Abstract: The strategy of improving the group delay in analog filters through the modification of conventional characteristic polynomials is a concept reported in advanced filter design literature. However, at present, this idea has only been approached from a theoretical perspective, validated by numerical or electrical simulations but not experimentally verified. This paper is precisely devoted to exploring the viability of physically realizing this idea. Because most of the references that deal with this topic consider the case of Chebyshev filters, this type of filters is also considered in our experimental validation. In our proposal, a synthesis based on FDNR topology (frequency-dependent negative resistor) is preferred over other circuit design strategies due to its low sensitivity. In order to verify the physical realization capability of this type of filter, the experimental results of a fifth-order Chebyshev filter implemented by using commercially available JFET op-amps TL082 are reported. In this case study, the frequency (magnitude and group delay) and time (step) responses of the conventional filter are contrasted with those of the modified filter, demonstrating that the experimental results accord with the theoretical background. PubDate: 2019-07-01

Abstract: A high energy-efficiency tri-level switching scheme for successive approximation register converters (SAR ADCs) is presented. The most significant bit-splitting digital to analogue converter and the least significant bit-down technique are combined in this work. The proposed scheme achieves 99.76% saving in switching energy and 75% area reduction compared with the traditional scheme. Besides large switching energy saving, the common mode voltage keeps constant except the LSB conversion, which reduces the dynamic offset of the comparator. PubDate: 2019-07-01

Abstract: This paper investigates relation between injection signaling and the lock range of relaxation oscillators. We show that lock range is determined by the effective injection signals of Volterra circuits contributed by both external injection signals and the nonlinearity of oscillators. The larger the harmonic tones of injection signals and the higher the degree of the nonlinearity of oscillators, the larger the effective injection signals subsequently the larger the lock range. We further show in order to maximize the contribution of external injection signals, injection phase needs to be \(\pi /2\) , valid for oscillators with either single or multi-tone injections. Moreover, we show to maximize lock range, the duty cycle of injection signals needs to be 50%. Finally, we show the phase noise of relaxation oscillators has a similar profile as that of harmonic oscillators. The quality factor of relaxation oscillators is smaller as compared with that of harmonic oscillators. The higher the degree of the nonlinearity of the relaxation oscillator, the smaller the quality factor of the relaxation oscillator subsequently the higher the phase noise. The theoretical findings on the lock range of relaxation oscillators are validated using the simulation results of a dual-comparator relaxation oscillator designed in TSMC 180 nm 1.8 V CMOS technology. PubDate: 2019-07-01

Abstract: A dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect, process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of power, delay, noise and robust against parameter and process corner variations. PubDate: 2019-07-01

Abstract: A low-pass fractional-order filter topology based on a single metal oxide semiconductor transistor is presented in this Letter. The filter is realized using a fractional-order capacitor fabricated using multi-walled carbon nanotubes. The electronic tuning capability of the filter’s frequency characteristics is achieved through a biasing current source. Experimental results are presented and compared with the theory. PubDate: 2019-07-01

Abstract: This paper reports a three-stage four-way power amplifier for 94 GHz image radar systems in 90 nm CMOS technology. The PA comprises a common-source (CS) input stage and a CS gain stage with wideband π-match input, inter-stage and output networks, followed by a four-way CS output stage using miniature dual-Y divider and combiner. Inductive shunt–shunt feedback technique is used at both the input and gain stages to enhance gain, which in turn leads to a higher output power (Pout) and power-added efficiency (PAE). At each branch’s input terminal (i.e. the drain terminal of the parallel CS output stage), the dual-Y current combiner can convert the serial RL load to the optimal load impedance (corresponds to the optimal Pout and PAE) of the output stage transistors. At 94 GHz, the PA achieves power gain of 16.5 dB, Pout of 16.5 dBm, and PAE of 18.3%, one of the best results ever reported for a W-band PA in 90 nm CMOS. The excellent performance of the CMOS PA indicates that it is suitable for 94 GHz image radar transceivers. PubDate: 2019-07-01

Abstract: A high-performance temperature-compensated crystal oscillator (TCXO) is presented. This paper proposes a new temperature sensor with a Σ–Δ analog to digital converter, and a voltage-controlled crystal oscillator, respectively, using two sets of independent power supply. The presented TCXO is implemented in a 0.35 μm 2P3 M standard complementary metal-oxide semiconductor process at a power supply of 3.3 V, and the total power dissipation is 21 mW. Measurement results indicate that the designed TCXO achieves ± 16 ppm output frequency tuning range and 135, − 141 dBc/Hz phase noise at 1, 10 kHz frequency offset, respectively, by using a 40 MHz fundamental AT-cut crystal resonator. With the temperature compensation, the frequency deviation is within ± 0.28 ppm over − 40 °C to 85 °C. PubDate: 2019-07-01

Abstract: In this letter, the effects of number of quantization levels are studied in the airborne digital radio frequency memory (DRFM). The artificial signal, produced by DRFM, has quantized amplitude that results in different cross-correlations (with respect to the real target echo signal), when correlated by continuous reference signal. The proposed method includes a technique to release from the estimation of amplitude fluctuations. Then, a closed-form expression is presented for likelihood ratio test discrimination. Simulation results prove the efficiency and robustness of the proposed method. PubDate: 2019-07-01

Abstract: This contribution aims at incorporating leakage control transistors (LCTs) in differential cascode voltage swing logic (DCVSL) to reduce leakage and is named as L-DCVSL. The concept multi threshold is also introduced in LCTs and resulting static, dynamic and enhanced DCVSL variants are referred as MTL-DCVSL, MTL-dyDCVSL and MTL-EDCVSL. The performance at 90 nm, 65 nm, and 45 nm technology nodes is investigated using SymicaDE tool. Two input exclusive OR/NOR (XOR2/XNOR2) gate is used to illustrate the proposed technique due to its extensive use in arithmetic cores. The leakage current is examined in all the examples and it is found that leakage current decreases with scaling down of geometry. Maximum saving in leakage current is observed to be 81.27% while minimum is 44.18% for MTL-DCVSL. Similar observations for MTL-dyDCVSL and MTL-EDCVSL are (12.24%, 9.52%)/(33%, 66.04%) and (16.06%, 61.67%)/(37.11%, 78.45%) respectively for precharge/evaluate state. Effect of temperature is also investigated and it is found that leakage current in both static and dynamic configurations of DCVSL follows a directly proportional behaviour with respect to temperature. PubDate: 2019-07-01

Abstract: This study focused on the design principle and implementation of a high-frequency, wide-range frequency synthesizer by using a dual control path phase-lock loop (PLL) and a varactorless oscillator controlled by inductive–capacitive (LC-type) voltage (i.e., a voltage-controlled oscillator, VCO). Without a varactor in the LC tank, the tuned-transducer oscillator with Q-enhanced functionality can easily arrive at the requirements of high-frequency wide-range low-noise operations. We utilized a difference tuned varactorless VCO to create two different KVCOs and applied it to a dual control path PLL architecture to obtain wide tuning range and more favorable phase noise. In addition, a high-speed current-mode logic divider was employed given its high speed (because of the use of a transformer inductor), extremely high operation frequency, and wide-range. The proposed PLL was assembled using the standard 0.13-μm CMOS technology on a 0.95 × 1.05 mm2 chip. The PLL dissipated 40 mW at a 1.2 V supply. The measurement of phase noise at 17.64 GHz was − 98.12 dBc/Hz at a 1 MHz offset. PubDate: 2019-07-01

Abstract: This paper presents a new digital predistortion (DPD) technique for wide band applications. Digital predistortion is the most useful linearization technique to reduce power amplifier (PA) nonlinearity effects due to its high flexibility and low complexity. However, this technique requires high performances ADC to digitize the feedback signal whose bandwidth is equal to several times the original bandwidth due to spectral regrowth generated by the PA nonlinearity. This point represents one of the main bottlenecks for the deployment of the wideband LTE-A standard. The method proposed in this paper calculates the DPD coefficients iteratively using an ADC with a fixed bandwidth equal to the original bandwidth. The proposed method has been simulated and compared with other methods using Matlab. Simulation results show that the proposed method has almost the same performance as the other methods with an ACPR of − 60 dB. Moreover, it reduces considerably the constraints on the ADC and the power calculation resources. PubDate: 2019-07-01

Abstract: Current-mode signaling significantly is known for increasing the bandwidth of on-chip interconnects and reduces the overall propagation delay. In this paper feature of current mode interconnects is exploited for investigating the performance of RLC equivalent ReffCT mathematical delay model of interconnects. This is due to a simple RC interconnects model which results a significant error in delay estimation. Due to this equivalency the non ideal effect of inductive behavior at high frequencies and scaled technologies can be suppressed. The dominance of inductance effect is optimized by Simulative Sweep Analysis Techniques (SSAT). Accuracy is verified by analytical and SPICE simulation results. The performance of delay model is further estimated for voltage and current mode interconnects. When test results are estimated with voltage and current mode systems, it is observed that the equivalent model is superior to the traditional Elmore and Sakurai delay model. PubDate: 2019-07-01

Abstract: This paper proposes a novel approach of analog circuit soft fault diagnosis utilizing matrix perturbation analysis. This method establishes an output response square matrix whose elements will change if circuits fail. Fault can be diagnosed via comparing the difference between the fault-free output matrix and the faulty. According to matrix theory, matrix spectral radius and perturbation matrix m1 norm are utilized to describe the difference. Differing from artificial intelligence algorithms, it is all completely unnecessary to train samples, and can be applied to more complex circuit diagnostics with fewer test nodes. Fault diagnosis, fault location and parameter identification can be realized by quadratic curve fitting in single fault mode. Experiments confirm the feasibility and correctness of this method. PubDate: 2019-07-01

Abstract: This article explains about the design of a new low power 11T SRAM cell. In this proposed method, two voltage sources are used, one is connected to the bit line and the other is connected to the bit bar line respectively in order to eliminate the swing voltage at the output nodes of the bit and bit bar lines. When the SRAM cell is in working mode the dynamic power dissipation is reduced by minimizing the swing voltage. Self-controllable voltage level is a technique in which PMOS transistor acts as a switch and NMOS transistors act as a resistors coupled in series reduces leakage current when the transistors change its state from sleep to active and vice versa. Reduce in leakage current causes the diminution in static power dissipation. To avoid the data retention difficulty, maximum voltage is supplied to the circuit during the active mode and reduced voltage is supplied during the stand-by mode. By using Synopsys EDA tool, all simulation results of power dissipation, delay, transistor utilization, power delay product and energy-delay product of the proposed 11T SRAM cell and other existing models of SRAM cell has been carried out in 30 nm CMOS technology. PubDate: 2019-07-01