Abstract: This paper implements a 125 level asymmetric cascaded multilevel inverter using fuzzy logic which is used in the dynamic voltage restorer. The inverter is designed with a reduced number of switches. The higher switching frequency is defined for the better performance of the multilevel inverter. The 125 level output is obtained in this proposed approach with only twelve switches and six voltage sources. By changing the switching frequency, the proposed output voltage level is obtained in the inverter. The paper is organized into two phases. In the first step the design of 125 level inverter is proposed, and in the second phase, the power quality improvement using the designed inverter is discussed. The proposed design of an inverter is implemented for dynamic voltage restorer solves the power quality problems such as are voltage sag, voltage swell, and harmonics. The power quality issue mitigation performance is increased with the proposed 125 level inverter. The enrichment of the proposed design is investigated using the comparison of existing works. The proposed work is implemented in the Matlab/Simulink environment. PubDate: 2019-12-01

Abstract: A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency fabricated by IHP’s 130 nm SiGe BiCMOS process is proposed. Instead of traditional on-chip metal–insulator–metal capacitor, a modified vertical parallel plate capacitor is utilized as the pumping capacitor, which owns a breakdown voltage higher than 84 V and an improved capacitance density of 1.92 fF/μm2. Thus, the output voltage and chip size of charge pump circuit are not limited by the pumping capacitor. To further improve the voltage pumping efficiency and make the circuit suitable for low voltage operation, the threshold voltage and the body effect coefficient is eliminated by using a dynamic control to both the charge transfer switches and the MOSFETs body voltages. Simulated result of a 35-stage charge pump circuit with an output voltage higher than 100 V is demonstrated. A 7-stage charge pump circuit with an output voltage of 13.8 V and a pumping efficiency of 75%, higher than the traditional Dickson’s charge pump circuits, is fabricated and measured. PubDate: 2019-12-01

Abstract: In this paper, a new memristive diode bridge-based RC hyperjerk circuit is proposed. This new memristive hyperjerk oscillator (MHO) is obtained from the autonomous 4-D hyperjerk circuit (Leutcho et al. in Chaos Solitons Fractals 107:67–87, 2018) by replacing the nonlinear component (formed by two antiparallel diodes) with a first order memristive diode bridge. The circuit is described by a fifth-order continuous time autonomous (‘elegant’) hyperjerk system with smooth nonlinearities. The dynamics of the system is investigated in terms of equilibrium points and stability, phase portraits, bifurcation diagrams and two-parameter Lyapunov exponents diagrams. The numerical analysis of the model reveals interesting behaviors such as period-doubling, chaos, offset boosting, symmetry recovering crisis, antimonotonicity (i.e. concurrent creation and destruction of periodic orbits) and several coexisting bifurcations as well. One of the most attractive features of the new MHO considered in this work is the presence of several coexisting attractors (e.g. coexistence of two, three, four, five, six, seven, or nine attractors) for some suitable sets of system parameters, depending on the choice of initial conditions. Accordingly, the distribution of initial conditions related to each coexisting attractor is computed to highlight different basins of attraction. Laboratory experimental measurements are carried out to verify the theoretical analysis. PubDate: 2019-12-01

Abstract: This research paper reports a novel design for third order chaotic and hyperchaotic oscillator with cubic nonlinearity using single operational trans-resistance amplifier (OTRA) and few passive elements. The key nonlinear dynamical characteristics in terms of sensitivity, divergence, equilibrium point and Lyapunov exponent are recorded in this literature. The operational activity of the proposed oscillator based on OTRA is integrated using 0.25 µm TSMC CMOS parameter. For the generation of hyperchaotic oscillator, an external capacitor is added to the third order chaotic oscillator. To justify the theoretical nonlinear dynamics of proposed chaotic oscillator, PSPICE simulation by using CMOS based OTRA and experimental investigation using IC AD844 based OTRA are well implemented. PubDate: 2019-12-01

Abstract: It is well known that timing jitter can degrade the bit error rate of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (1) data dependent jitter, (2) random jitter, and (3) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations. PubDate: 2019-12-01

Abstract: This study presents a noise-canceled transimpedance amplifier (TIA) for optical receivers. The proposed structure consists of a shunt feedback common source amplifier as an input stage followed by two regulated cascodes (RGC) and finally a differential to the single-ended amplifier at the output stage. By exploiting the noise-canceling technique at the input stage, 31.8% of the total output noise is canceled. In addition, the auxiliary path’s RGC circuit, as it has a low input impedance, is utilized to cancel out the photodiode (PD) large parasitic capacitance at the input stage. The proposed TIA along with post amplifiers, including packaging components, are simulated in TSMC 90 nm RF CMOS technology at the post-layout level. The TIA average input-referred current noise is equal to \(9.5\;{\text{pA}}/\sqrt {\text{Hz}}\). The PD capacitance is considered as 325 fF for all simulations. The transimpedance gain is equal to 60 dBΩ and the 3-dB bandwidth is equal to 7 GHz. The power consumption of the proposed TIA is 3.6 mW from a 1.2 V supply voltage. The TIA occupies a chip area of 0.036 mm2. PubDate: 2019-12-01

Abstract: In this paper, a peak efficiency tracking technique to improve the efficiency of switched capacitor (SC) DC–DC converters as the load varies is presented. A peak efficiency tracking circuit based on feedback control over the switching frequency is implemented for this scope. The basic idea of the proposed technique is to adjust the switching frequency according to the load. The technique is successfully implemented in a SC DC–DC converter to be embedded in detector pixels for the Large Hadron Collider (LHC) experiment at the Conseil Européen pour la Recherche Nucléaire (CERN) of Geneve. It is realized in 65 nm bulk CMOS technology with an occupied area of 1.31 mm2. This converter provides an 800 mV output voltage from a 1.2 V supply. The load of the DC–DC converters is modeled as a resistor, RLOAD, that has 4 Ω nominal value but it can range from 2.67 up to 10 Ω. At 10 Ω RLOAD, a 6% efficiency improvement is reached with respect to the typical approach consisting in keeping constant the switching frequency at the optimum value for RLOAD nominal value. PubDate: 2019-12-01

Abstract: MEMS capacitive switches have longer lifetimes compared to other types of metal-to-metal switches, and when placed on the membrane on the transmission line, they can easily return to the up-state due to a dielectric layer. They also transmit the input signal with more power and frequency and therefore, they are better than metal-to-metal switches. In this paper, first three switches were considered as the basic structures. Then, in order to demonstrate the credibility and high quality of the simulations, the same switches were simulated. The obtained results are very close to the results of fabrication of these switches. In the next step, with the presentation of three new structures, stimulation voltage, stress, switching time and isolation were improved in four steps. The mechanical simulation of the switch was performed to determine the amount of displacement, the amount of stress and the resonant frequency using the COMSOL software. In addition, electrical simulation of the switch was performed to obtain the S-parameter using the HFSS software. The simulation results demonstrate that the isolation is 57–66 dB and the insertion loss is 0.3–2 dB in the desired frequency band (1–50 GHz). Using new spring structures, the actuation voltage was reduced from 4.8 V in basic structures (the smallest in three structures) to 2.4 V in new structures, which is considered excellent. In order to increase the lifetime of the switch, the stress in the new switches is reduced from 12 to 4.5 MPa compared to the basic switches. PubDate: 2019-12-01

Abstract: The numeric solutions to nonlinear differential equations play a great role in many areas of engineering. In many cases all that is desired an accurate solution to a few points which can be calculated in a short time period. This study provides an exact solution to nonlinear ordinary differential equations arising from electrical circuit representation. This achievement is due to the application of the generalized trial equation. The exact solution gives a good analytic solution to a nonlinear equation that describes the action of a nonlinear electrical circuit. It is suggested that the methodology used herein may be useful in the study of other nonlinear problems described by differential equations approximated by an appropriate solution. In particular, the exact solution may be applied to the study of the cubic nonlinear circuit and system applications to prevent the difficulties that may arise due to approximation methods. The newly generated method that produces an exact solution tested for a pendulum, Poisson–Boltzmann, Duffing like electrical circuit applications. PubDate: 2019-12-01

Abstract: The HEVC video coding standard supports different transform sizes ranging from 4-point to 32-point. In fact, multiple transform sizes improve coding efficiency, but increase as well the computational complexity. Hardware decoders apply different techniques to satisfy real-time requirements. This paper describes a novel design methodology of a unified 2D inverse core transform IICT. The hardware architecture is based on a 1D-IICT block and a transpose buffer FIFO memory used to store the intermediate values of 1D transform. All this process is controlled in such a way to reduce the hardware and memory resources. To support the different transform sizes, matrix multiplications are simplified based on transform blocks decomposition into fixed-size sub-blocks in previous works. The architecture was developed for an FPGA device. Synthesis results on Startix III FPGA device show that the proposed design, operating at 266 MHz, is sufficient to decode high resolution videos using only 10% of total pins and about 33% of the hardware resources offered. PubDate: 2019-12-01

Abstract: This paper proposes an efficient converter for the usage of hybrid renewable energy sources and reduced switching loss in the Micro Grid associated frameworks. The work resulted in a DC–DC converter for module integration and maximum power point tracking with an efficient adaptive control scheme. The proposed control scheme is a combined execution of both the adaptive grasshopper optimization algorithm (AGOA) and artificial neural network (ANN) named as AGONN strategy. In the proposed strategy, the AGOA plays out the evaluation technique to set up the correct control signals for the system and develops the control signals database for the offline way subject to the power exchange between source side and the load side. Moreover, to train the ANN system for the online way, the achieved dataset is utilized and it drives the control method in less execution time. Also, the objective function is characterized by the system data subject to equality and inequality constraints. The constraints are the accessibility of the renewable energy sources, power demand and the state of charge of storage elements. Batteries are used as an energy source, to balance out and allow the renewable power system units to continue running at a steady and stable output power. By then, the proposed show is executed in MATLAB/Simulink working platform and the execution is surveyed with the current methods. PubDate: 2019-12-01

Abstract: A ripple-based adaptive on-time controlled buck converter with slope balance technique is presented in this paper. The slope balance technique provides a fixed switching frequency. A 4-bit single-slope analog-to-digital converter (ADC) was used to fix switching frequency when power supply was from 3.3 to 4.5 V. The slope balance technique is proposed to achieve an adaptive on-time control and without extra clock-controlled circuits and current sensing circuits. The input voltage can be predicted from the adaptive on-time by using 4-bit single-slope ADC control. Measurement results show that switching frequency is 1.448 and 1.438 MHz when load current is 200 and 1000 mA, respectively. The proposed buck converter was fabricated in 0.35 μm CMOS technology with a supply voltage of 4.5 V. The output voltage was measured to be 1.2 V and the load current range was determined to range 200–1000 mA. PubDate: 2019-12-01

Abstract: A low noise figure (NF) and high power gain (S21) 3–10 GHz ultra-wideband (UWB) low noise amplifier (LNA) in 65 nm CMOS technology is proposed for UWB system which has a high figure of merit. A shunt–shunt resistive feedback technique is used to achieve wideband input impedance matching. A differential current-reused structure is used to achieve high common noise suppression and low power consumption. The implemented LNA achieves a high and flat aS21 of 15.6 ± 1.07 dB with an input return loss (S11) which is better than − 8.7 dB and a low NF of 2.99 ± 0.18 dB at frequencies of 3–10 GHz. The measured input third-order intermodulation point (IIP3) is − 5.7 dBm at 6 GHz. PubDate: 2019-12-01

Abstract: We introduce a unique chaotic flow with three terms expressed by \( \dddot x + abx = d \sinh \left( {\dot{x} + c\ddot{x}} \right) \). This minimal Jerk model is presented as a novel 3-D chaotic system consisting uniquely of two linear terms and single hyperbolic sine nonlinearity. The presence of coexisting routes to chaos in the numerical studies justifies the appearance of multiple solutions in some ranges of parameters. For instance, up to six different coexisting solutions (a pair of period-5 limit cycles and two pairs of chaotic attractors) have been tracked. Furthermore, the generalized form of the introduced Jerk system is synthesized with a parametric nonlinearity of the form \( \phi_{k} \left( X \right) = 0.5\left( {exp\left( {k\left( {\dot{x} + c\ddot{x}} \right)} \right) - exp\left( { - \left( {\dot{x} + c\ddot{x}} \right)} \right)} \right) \). Based on this generalized form, and judiciously adjusting the parameter \( k \), an in-depth description of the dynamics of the system at the symmetry boundaries is carried out. Hysteresis and parallel bifurcation behaviors reflect the presence of multiple asymmetric solutions (e.g. the coexistence of four asymmetric attractors) in the new model. It should be mention that the presence of six coexisting attractors reported in this work is rarely shown in third-order systems and therefore represents an enriching contribution to the study of dynamic systems in general. Finally, some PSpice simulations and laboratory tests of the proposed circuit are included. PubDate: 2019-12-01

Abstract: This paper presents an all-digital duty-cycle corrector (DCC) for integrated phase noise (IPN) improvement in phase-locked loops (PLL). The proposed DCC implies a duty cycle adjustor (DCA) that adjusts the output duty regardless of the input duty. The duty range of the proposed DCA is extended by the feedback loop code which is generated by reducing the duty-cycle error (DCE) within a feedback loop using a proposed cyclic time-to-digital converter. The test chip was fabricated in a 40-nm CMOS process, and it occupied an active area of 0.039 mm2. The measured DCE of the proposed DCC is less than 1.16%. In addition, the measurements were performed by applying the proposed DCC along with a reference doubler to a PLL. The measurement results show an approximately 21-dB reduction in reference spurs with 7.29 dB and 0.54° improvement in in-band PN and overall IPN of PLL, respectively. PubDate: 2019-12-01

Abstract: High progresses in the field of power electronic create an appropriate bed to introduce new and upgraded multilevel inverter topologies. Such these topologies contain remarkable inherent advantages like: high quality staircase sinusoidal output voltage, low number of switches, low peak inverse voltage, et cetera. In this paper, a novel modular asymmetrical multilevel inverter is proposed to reduce the number of inverter’s components, and accordingly make a cost-effective structure with excellent voltage-step creation. In accordance with the configuration of utilized switches and magnetite of DC voltage source, the proposed structure can provide a high-step staircase sinusoidal voltage without high increase of semiconductors. Consider this; symmetrical condition of the proposed structure also takes low number of switches as compared to other symmetrical structures. Finally, both the MATLAB/SIMULINK and experimental results have confirmed the accurate operation and voltage-step creation capability of the suggested multilevel inverter. PubDate: 2019-12-01

Abstract: A flipped voltage follower structure based on a dynamic current boosting technique is proposed which enables the fast-transient behavior. It is applied to an output capacitor-less low-dropout (LDO) regulator to improve the output transient response and reduce the over/undershoots of the output voltage when the load current or the input voltage is suddenly changed. The proposed low-dropout regulator is simulated in 0.18 μm CMOS technology, which the output voltage is regulated at 1 V with a dropout voltage of about 114 mV. The output voltage over/undershoot amplitudes of the proposed LDO are obtained in 99.52/551.8 mV with the settling time of fewer than 1.3 μs for the load current changes from 0.1 to 100 mA with 200 ns rise/fall times. PubDate: 2019-12-01

Abstract: We investigate the dynamics of a simple jerk circuit where the symmetry is broken by forcing a dc voltage. The analysis shows that with a zero forcing dc voltage, the system displays a perfect symmetry and develops rich dynamics including period doubling, merging crisis, hysteresis, and coexisting multiple (up to six) symmetric attractors. In the presence of a non-zero forcing dc voltage, several unusual and striking nonlinear phenomena occur such as coexisting bifurcation branches, hysteresis, asymmetric double scroll strange attractors, and multiple coexisting asymmetric attractors for some appropriate sets of system parameters. In the latter case, different combinations of attractors are depicted consisting for instance of two, three, four, or five disconnected periodic and chaotic attractors depending solely on the choice of initial conditions. The investigations are carried out by using standard nonlinear analysis tools such as Lyapunov exponent plots, bifurcation diagrams, basins of attraction, and phase space trajectory plots. The theoretical results are checked experimentally and a very good agreement is found between theory and experiment. PubDate: 2019-12-01

Abstract: Brain consists of a network of millions of neurons and the neural activities of the brain are clearly pictured in its signal, electroencephalogram (EEG). Many pathological conditions of brain can be studied in detail by inspecting the EEG signal in detail rather than just visual inspection. Non linear analysis has proved to be an efficient method for exploring the subtle information embedded in EEG. Approximate entropy and sample entropy are utilized in this study for comparing EEGs of patients with a neurological disease called encephalopathy, with normal EEGs. Both entropies were found to be significantly less (p < 0.01; independent sample t test) for encephalopathy group than normal healthy controls. Support vector machine, multilayer perceptron and random forest classifiers have been employed for identifying disease groups based on the EEG entropies and their performance were evaluated. Random forest classifier gave the maximum accuracy of 90% while multilayer perceptron and SVM classifier gave an accuracy of 87% and 84% respectively. The optimum performance was obtained by combining both approximate entropies and sample entropies as features to the classifiers, than using individual set of features. Thus, this work emphasizes that entropies of EEG are good bio-markers for the diagnosis of encephalopathy and that non linear analysis techniques should be employed for analyzing EEG signals. PubDate: 2019-12-01

Abstract: An output capacitor-less low-dropout (OCL-LDO) voltage regulator with dual active feedback paths is presented in this paper. The dual active feedbacks provide frequency compensation and spike voltage suppression. Two feedback loops are formed by capacitors Cc and Ca, respectively. The capacitor Ca path detects output voltage to suppress undershoot and overshoot during load transient. The frequency compensation is achieved by capacitor Cc, which helps the LDO regulator not only improve stability, but also enhance transient response without large current consumption. The total utilized capacitance values are only 1.5 pF. The proposed OCL-LDO was fabricated in 0.18 μm CMOS technology with supply voltage of 1.8 V. The LDO consumes 21 μA of quiescent current and the chip area is 0.47 mm × 0.49 mm. The measured output voltage difference is 90 mV when the load current is increased from 50 μA to 100 mA with CL= 100 pF and recovery time less than 1 μs. The power supply rejection is − 51.7 dB at 1 kHz. PubDate: 2019-12-01