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Publisher: Springer-Verlag (Total: 2352 journals)

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 Analog Integrated Circuits and Signal ProcessingJournal Prestige (SJR): 0.211 Citation Impact (citeScore): 1Number of Followers: 7      Hybrid journal (It can contain Open Access articles) ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030 Published by Springer-Verlag  [2352 journals]
• A novel approach for noise tolerant energy efficient TSPC dynamic circuit
design
• Abstract: A dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect, process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of power, delay, noise and robust against parameter and process corner variations.
PubDate: 2019-04-23

• Velocity deception jamming discrimination using quantization effect
• Abstract: In this letter, the effects of number of quantization levels are studied in the airborne digital radio frequency memory (DRFM). The artificial signal, produced by DRFM, has quantized amplitude that results in different cross-correlations (with respect to the real target echo signal), when correlated by continuous reference signal. The proposed method includes a technique to release from the estimation of amplitude fluctuations. Then, a closed-form expression is presented for likelihood ratio test discrimination. Simulation results prove the efficiency and robustness of the proposed method.
PubDate: 2019-04-16

• A Ku-band dual control path frequency synthesizer using varactorless Q
-enhanced LC -type VCO
• Abstract: This study focused on the design principle and implementation of a high-frequency, wide-range frequency synthesizer by using a dual control path phase-lock loop (PLL) and a varactorless oscillator controlled by inductive–capacitive (LC-type) voltage (i.e., a voltage-controlled oscillator, VCO). Without a varactor in the LC tank, the tuned-transducer oscillator with Q-enhanced functionality can easily arrive at the requirements of high-frequency wide-range low-noise operations. We utilized a difference tuned varactorless VCO to create two different KVCOs and applied it to a dual control path PLL architecture to obtain wide tuning range and more favorable phase noise. In addition, a high-speed current-mode logic divider was employed given its high speed (because of the use of a transformer inductor), extremely high operation frequency, and wide-range. The proposed PLL was assembled using the standard 0.13-μm CMOS technology on a 0.95 × 1.05 mm2 chip. The PLL dissipated 40 mW at a 1.2 V supply. The measurement of phase noise at 17.64 GHz was − 98.12 dBc/Hz at a 1 MHz offset.
PubDate: 2019-04-15

• 2.4 GHz wake-up receiver with suppressed substrate noise coupling
• Abstract: The switching noise generated in digital circuits propagates through conductive silicon substrate to analog circuits in a mixed-signal CMOS LSI. Substrate noise coupling may degrade the performance of the analog circuits, and may result in a fault operation of the mixed-signal LSI in the worst-case. In this paper, the substrate noise coupling between the clock recovery circuit and the input port of the envelop detector in a low-power wake-up receiver (WuRx) was investigated experimentally. The propagation path of the substrate noise coupling was clarified by comparing the experimental results with the circuit simulations on the basis of an equivalent circuit model. The design of the WuRx was modified on the basis of the findings to suppress the substrate noise coupling. The fabricated WuRx successfully operated a 100-kbps PWM signal with a carrier frequency of 2.4 GHz, and the effectiveness of the noise coupling suppression recipe was confirmed.
PubDate: 2019-04-15

• A low energy switching scheme for SAR ADC with MSB-splitting DAC structure
• Abstract: A high energy-efficiency tri-level switching scheme for successive approximation register converters (SAR ADCs) is presented. The most significant bit-splitting digital to analogue converter and the least significant bit-down technique are combined in this work. The proposed scheme achieves 99.76% saving in switching energy and 75% area reduction compared with the traditional scheme. Besides large switching energy saving, the common mode voltage keeps constant except the LSB conversion, which reduces the dynamic offset of the comparator.
PubDate: 2019-04-13

• A 96.88% area-saving and 99.72% energy-reduction switching scheme for SAR
ADC with a novel two-step quantisation technique
• Abstract: This paper presents a novel area-saving and energy-efficient switching capacitor structure for successive approximation register analog-to-digital conversions, which uses a two-step quantisation logic control switching scheme. The two steps are coarse and fine quantisation respectively. During the coarse quantisation, there is no power consumption at the first two cycles. The fine quantisation does not increase the number of binary capacitors while consumes no energy. Therefore, the two-step quantisation switching scheme can significantly reduce both the power consumption and the capacitor area. Simulation results show that the structure can reduce the average energy and the capacitor area by 99.72% and 96.88% respectively over the conventional method.
PubDate: 2019-04-12

• Optimal utilization of renewable energy sources in MG connected system
with integrated converters: an AGONN Approach
• Abstract: This paper proposes an efficient converter for the usage of hybrid renewable energy sources and reduced switching loss in the Micro Grid associated frameworks. The work resulted in a DC–DC converter for module integration and maximum power point tracking with an efficient adaptive control scheme. The proposed control scheme is a combined execution of both the adaptive grasshopper optimization algorithm (AGOA) and artificial neural network (ANN) named as AGONN strategy. In the proposed strategy, the AGOA plays out the evaluation technique to set up the correct control signals for the system and develops the control signals database for the offline way subject to the power exchange between source side and the load side. Moreover, to train the ANN system for the online way, the achieved dataset is utilized and it drives the control method in less execution time. Also, the objective function is characterized by the system data subject to equality and inequality constraints. The constraints are the accessibility of the renewable energy sources, power demand and the state of charge of storage elements. Batteries are used as an energy source, to balance out and allow the renewable power system units to continue running at a steady and stable output power. By then, the proposed show is executed in MATLAB/Simulink working platform and the execution is surveyed with the current methods.
PubDate: 2019-04-11

• Optimum test point selection method for analog fault dictionary techniques
• Abstract: Fault dictionary has two types of online and offline calculation. Online calculation is simple, but offline is excessive and time-consuming. In order to reduce the computation time and dimension of fault dictionary, optimal test points selection is very essential. So, the main purpose, fault isolation, is achieved in a short time. In this paper a new efficient method to select an optimum set of test points for fault diagnosis is proposed. At the first, a fault-isolated table is constructed to pick out the special test points from the candidates. Then, the isolation ability of special test points has been considered. If they can’t isolate all of faults, the fault dictionary is rearranged. Therefore, the special test points and isolated faults are eliminated from the table of fault dictionary. In this step, the test point with more single fault is added to special test points. This step is repeated to isolate all of faults. The proposed method is applied on two-stage operational amplifier. By this method, all of faults for this structure are isolated. The computation requirements are very simple than the other methods. In this circuit, the 0.045 s is needed to isolate all of circuit faults. According to the results, it’s clear that the method is a good solution to minimize the size of the test points set. Also, it can be a practical method for medium and large scale systems.
PubDate: 2019-04-10

• A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching
using a novel effective asynchronous control circuitry
• Abstract: Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work describes such a structure through the use of a novel low offset comparator thereby reducing the non-linearity performance along with significant improvement in energy-delay metric. A high speed control circuitry is introduced to improve the overall frequency of operation of SAR-ADC minimizing its speed limitation. Capacitive based digital-to-analog converter is used that switches in alternate cycles to reduce the static power dissipation. The ADC architecture is designed in 45-nm CMOS technology at layout of $$0.0139 \,{\hbox {mm}}^{2}$$ . The extracted results show that the proposed design is a reliable framework to ascertain the effectiveness of SAR-ADC with a faster performance. The results demonstrate an improvement of 47.75% in figure-of-merit. SNDR and SFDR are found to be 57.2 dB and 61.4 dB respectively at input frequency of 10 MHz. The sampling frequency is taken as 1 GHz with a power supply of 1 V.
PubDate: 2019-04-09

• W-Band power amplifier with high output power and power-added efficiency
in 90 nm CMOS
• Abstract: This paper reports a three-stage four-way power amplifier for 94 GHz image radar systems in 90 nm CMOS technology. The PA comprises a common-source (CS) input stage and a CS gain stage with wideband π-match input, inter-stage and output networks, followed by a four-way CS output stage using miniature dual-Y divider and combiner. Inductive shunt–shunt feedback technique is used at both the input and gain stages to enhance gain, which in turn leads to a higher output power (Pout) and power-added efficiency (PAE). At each branch’s input terminal (i.e. the drain terminal of the parallel CS output stage), the dual-Y current combiner can convert the serial RL load to the optimal load impedance (corresponds to the optimal Pout and PAE) of the output stage transistors. At 94 GHz, the PA achieves power gain of 16.5 dB, Pout of 16.5 dBm, and PAE of 18.3%, one of the best results ever reported for a W-band PA in 90 nm CMOS. The excellent performance of the CMOS PA indicates that it is suitable for 94 GHz image radar transceivers.
PubDate: 2019-04-08

• A broadband GaAs pHEMT low noise driving amplifier with current reuse and
self-biasing technique
• Abstract: A K/Ka-band two-stage low noise driving amplifier using a 0.15 μm GaAs pHEMT for low noise technology is designed and fabricated. In order to achieve broadband driving capability with low power consumption, current reuse technique is adopted to feed both transistors with the same DC power supply, which theoretically cuts the total current consumption in half. In addition, self-biasing technique is utilized to minimize both external power supply pads and chip footprint, which reduces the number of supply pads to a minimum of two (1 power pad and 1 ground pad). The circuit topology analysis and design procedures are also presented with an emphasis on noise figure and P1dB optimization. The low noise driving amplifier demonstrates a − 3 dB bandwidth of wider than 11 GHz, a power gain of 17 dB, an in-band mean noise figure of 2.2 dB and an in-band mean output P1dB of 6 dBm. The DC power consumption is 9.1 mA@3.3 V power supply. The chip size is 1 mm × 1.5 mm with only 1 external DC feed pad (3.3 V) and 1 ground pad (0 V). With the performance comparable to typical two-stage dual-bias low noise driving amplifier counterparts, the proposed MMIC is more attractive to chip/system users in volume-limited and power-contrained applications.
PubDate: 2019-04-01

• A survey of circuit-level soft error mitigation methodologies
• Abstract: Soft errors created due to propagation of single event transients are a significant reliability challenge in modern VLSI. With advances in CMOS technology scaling, circuits become increasingly more sensitive to transient pulses caused by energetic particles. This work reviews some popular circuit level SET mitigation techniques developed for combinational logic and compares them with respect to area, power and delay overheads.
PubDate: 2019-04-01

• A 20 GHz subharmonic injection-locked clock multiplier with mixer-based
injection timing control in 65 nm CMOS technology
• Abstract: This paper presents a 20 GHz subharmonic injection-locked clock multiplier (SILCM), which adopts a mixer based self-align injection timing control loop to guarantee the optimal injection point. In addition, to further improve the injection time accuracy and reduce the super, a V/I mismatch cancellation are utilized. Furthermore, a frequency-locked loop with a frequency-lock detection and enable control switch is employed to expand the injection-locked range and save power. Fabricated in a 65 nm CMOS technology, the SILCM can lock from 19.2 GHz to 23.2 GHz. It exhibits − 125.5 dBc/Hz phase noise at 1 MHz offset and consumes 8 mW under 1.2 V power supply. The measured root-mean-square jitter integrating from 0.1 kHz to 100 MHz is 106 fs and the reference spur is − 43 dB.
PubDate: 2019-04-01

• Ex-situ training of large memristor crossbars for neural network
applications
• Abstract: Memristor crossbar arrays carry out multiply–add operations in parallel in the analog domain, and can enable neuromorphic systems with high throughput at low energy and area consumption. Neural networks need to be trained prior to use. This work considers ex-situ training where the weights pre-trained by a software implementation are then programmed into the hardware. Existing ex-situ training approaches for memristor crossbars do not consider sneak path currents, and they may work only for neural networks implemented using small crossbars. Ex-situ training in large crossbars, without considering sneak paths, reduces the application recognition accuracy significantly due to the increased number of sneak current paths. This paper proposes ex-situ training approaches for both 0T1M and 1T1M crossbars that account for crossbar sneak paths and the stochasticity inherent in memristor switching. To carry out the simulation of these training approaches, a framework for fast and accurate simulation of large memristor crossbars was developed. The results in this work show that 0T1M crossbar based systems can be 17–83% smaller in area than 1T1M crossbar based systems.
PubDate: 2019-04-01

• Ultra-low voltage and low-power voltage-mode DTMOS-based four-quadrant
analog multiplier
• Abstract: This paper presents a new four-quadrant analog multiplier based on a dynamic threshold MOS (DTMOS). The attractive features of this DTMOS transistor-based multiplier are its supply voltages and total power consumption, which were determined as ± 0.2 V and 18.4 nW, respectively. In addition, the study found no influences of the bulk effect of the transistors used in the proposed multiplier circuit. The layout of the four-quadrant analog multiplier occupied an active area of 44.6 µm × 21.93 µm and was drawn using Cadence Environment software, while the post-layout simulation results were performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. All theoretical results and post-layout simulations confirmed the performance of the proposed circuit.
PubDate: 2019-04-01

• Modeling and sizing of non-linear CMOS analog circuits used in mixed
signal systems
• Abstract: In this paper, modeling of performance parameters and time efficient yet accurate sizing methodology of CMOS analog non-linear circuits have been proposed. The proposed modeling methodology generates empirical models of the non-linear circuit performance parameters in monomial or posynomial form, which is geometric programming (GP) compatible, as a function of the final design variables of the circuit (i.e. the width and length of the transistors). The proposed non-linear circuit sizing methodology, referred to as iterative geometric programming utilizes a correction factor for each of the GP compatible performance parameter models. These correction factors are updated using SPICE simulation after every iteration of the GP optimization. The proposed methodology takes advantage of GP optimization and at the same time it uses SPICE simulation to improve the design point by rectifying inaccuracies that may exists in the GP compatible performance models. Both the proposed methodologies have been validated in a 0.18 μm CMOS technology. The dynamic comparator and the bootstrap switch which are commonly used non-linear circuits in analog-mixed signal systems, have been used as the example circuits. It has been observed that the proposed sizing algorithm converges rapidly and give final design point with SPICE level accuracy higher than 99 %. The efficiency and the accuracy of the proposed algorithm has been numerically compared w.r.t. the sizing algorithm using evolutionary algorithm. It has been observed that the proposed algorithm gives much better results. Moreover, the proposed algorithm is hundreds times faster than that of the evolutionary algorithm.
PubDate: 2019-04-01

• An efficient end-to-end deep learning architecture for activity
classification
• Abstract: Deep learning is widely considered to be the most important method in computer vision fields, which has a lot of applications such as image recognition, robot navigation systems and self-driving cars. Recent developments in neural networks have led to an efficient end-to-end architecture to human activity representation and classification. In the light of these recent events in deep learning, there is now much considerable concern about developing less expensive computation and memory-wise methods. This paper presents an optimized end-to-end approach to describe and classify human action videos. In the beginning, RGB activity videos are sampled to frame sequences. Then convolutional features are extracted from these frames based on the pre-trained Inception-v3 model. Finally, video actions classification is done by training a long short-term with feature vectors. Our proposed architecture aims to perform low computational cost and improved accuracy performances. Our efficient end-to-end approach outperforms previously published results by an accuracy rate of 98.4% and 98.5% on the UTD-MHAD HS and UTD-MHAD SS public dataset experiments, respectively.
PubDate: 2019-04-01

• Buffer insertion for delay minimization in RLC interconnects using cuckoo
optimization algorithm
• Abstract: In this paper, cuckoo optimization algorithm (COA) as an efficient evolutionary algorithm is used for buffer insertion in digital circuits. Application of the COA to real problems and some benchmark functions has proven its capability of dealing with difficult optimization problems and shown its superiority in fast convergence and global optima achievement. The aim of the work is to reduce the propagation delay in resistance–inductance–capacitance (RLC) interconnects. Furthermore, inductance effects on optimal number and size of buffer are investigated. This work is performed in two case studies. Buffer insertion in RLC lines is done in case study-I. Buffer insertion in tree structured inductive interconnects is dealt in case study-II. The COA results show the considerable reduction in the propagation delay. Maximum percentage of reduction in delay is 59.78% for line, 67.67% for balanced tree and 63.75% for unbalanced tree respectively. Also, optimal area (size and number of buffers) is another result of paper that can lead to economical number of chips.
PubDate: 2019-04-01

• Low power W-band divide-by-3 injection-locked frequency dividers with wide
locking range in 90 nm CMOS
• Abstract: In this work, we demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower cross-coupled transistors and then inject the source terminals of the upper cross-coupled transistors. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower cross-coupled transistors. Due to the strong second harmonic signal (2finj) at the source terminals of the upper cross-coupled transistors, there are notable locked fundamental signals (finj) at the drain terminals of the upper cross-coupled transistors. ILFD31 occupies a chip area of 0.744 × 0.859 mm2 (i.e. 0.639 mm2), consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5–95.9 GHz). ILFD32 occupies a chip area of 0.87 × 0.775 mm2 (i.e. 0.674 mm2), consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8–109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.
PubDate: 2019-04-01

• Effect of PVT variations on differential-time signaling data link
architecture
• Abstract: In this paper, the effect of process, voltage and temperature (PVT) variation on the differential-time signaling (DTS) serial link architecture has been studied. An example of 65 nm CMOS 4-bit 6 Gb/s DTS serial link has been designed and simulated using 1.5 GHz as an input clock signal in order to study the effect of PVT variation on DTS architectures. Mont-Carlo simulations have been carried out for the designed link. The simulated link has been tested under different operating temperatures from 0 to 120 °C, the link achieves correct transmission for the temperature range from 0 to 80 °C without calibrating the delay lines against the temperature change. The voltage supply has been varied from 0.95 to 1.05 V in order to study the effect of the voltage supply variation. The simulated link achieves correct transmission for a voltage supply variation within ± 2.5% of the nominal value without calibrating the delay lines against the voltage supply change. Using the DTS architecture as a serial link tolerate an adequate amount of PVT variation as well as relaxes the design constrains of the calibration technique, which is required for the delay lines to ensure correct transmission.
PubDate: 2019-04-01

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