for Journals by Title or ISSN for Articles by Keywords help

Publisher: Springer-Verlag (Total: 2353 journals)

 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [7 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2353 journals]
• 94 GHz down-conversion mixer with gain enhanced Gilbert cell in
90 nm CMOS
• Authors: Yo-Sheng Lin; Chien-Chin Wang; Jay-Ming Liu
Pages: 1 - 11
Abstract: Abstract A 94 GHz down-conversion mixer for image radar sensors using standard 90 nm CMOS technology is reported. The down-conversion mixer comprises a double-balanced Gilbert cell with an LC-tank-oscillator-based RF transconductance stage load for conversion gain (CG) enhancement and noise figure (NF) suppression, two miniature planar baluns for converting the single RF and LO input signals to differential signals, and an IF amplifier. The mixer consumes 9.5 mW and achieves excellent RF-port input reflection coefficient (S11) of −27.2 dB at 94 GHz, and S11 smaller than −10 dB for frequencies of 83.6–110 GHz. That is, RF-port −10 dB input matching bandwidth is greater than 26.4 GHz. In addition, for frequencies of 75–100 GHz, the mixer achieves CG of 4.9–7.9 dB (the corresponding 3-dB CG bandwidth is greater than 25 GHz), LO–RF isolation of 38.5–44.7 dB and NF of 15.4–21.2 dB, one of the best CG, LO–RF isolation and NF results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of 2.6 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is promising for 94 GHz image radar sensors.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1019-y
Issue No: Vol. 93, No. 1 (2017)

• A multi-band low noise amplifier with strong immunity to interferers
• Authors: Zaira Zahir; Gaurab Banerjee; Mohamad A. Zeidan; Jacob A. Abraham
Pages: 13 - 27
Abstract: Abstract A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable $$\pi$$ network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip built-in-self-test circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point ( $$IIP_3$$ ) ranges from −15 to 0 dBm. Implemented in a 0.13  $$\upmu$$ m CMOS technology, the LNA occupies an active area of about 0.29 mm $$^2$$ . This design can be used for cognitive radio and other wideband applications, which require a dynamic configuration of the signal-to-intermodulation ratio, when sufficient information about the power and the location of the interferers is not available.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1020-5
Issue No: Vol. 93, No. 1 (2017)

• Low power PLL with reduced reference spur realized with glitch-free linear
PFD and current splitting CP
• Authors: K. K. Abdul Majeed; Binsu J. Kailath
Pages: 29 - 39
Abstract: Abstract This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1013-4
Issue No: Vol. 93, No. 1 (2017)

• 3.6 mw low power wireless RF receiver front end using creative
current recycle technique
• Authors: T. Damodara Venkata Appala Naidu; B. K. Madhavi; K. Lal Kishore
Pages: 41 - 47
Abstract: Abstract This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors Q5 and Q6. By using the creative current recycle technique circuit consumes 3.6 mW power with 1.2 V power supply. The operating frequency of the proposed structure is 2.4 GHz with 25 dB conversion gain and −13 dBm IIP3. The operating of the receiver front end is 2.4 GHz is used for IEEE 802.11a WLAN, Bluetooth, and ZigBee applications.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1034-z
Issue No: Vol. 93, No. 1 (2017)

• A 90–96 GHz CMOS down-conversion mixer with high conversion gain and
excellent LO–RF isolation
• Authors: Yo-Sheng Lin; Ming-Huang Kao; Hou-Ru Pan; Kai-Siang Lan
Pages: 49 - 59
Abstract: Abstract A 90–96 GHz down-conversion mixer for 94 GHz image radar sensors using standard 90 nm CMOS technology is reported. RF negative resistance compensation technique, i.e. NMOS LC-oscillator-based RF transconductance (GM) stage load, is used to increase the output impedance and suppress the feedback capacitance Cgd of RF GM stage. Hence, conversion gain (CG), noise figure (NF) and LO–RF isolation of the mixer can be enhanced. The mixer consumes 15 mW and achieves excellent RF-port input reflection coefficient of −10 to −36.4 dB for frequencies of 85–105 GHz. The corresponding -10 dB input matching bandwidth is 20 GHz. In addition, for frequencies of 90–96 GHz, the mixer achieves CG of 6.3–9 dB (the corresponding 3-dB CG bandwidth is greater than 6 GHz) and LO–RF isolation of 40–45.1 dB, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of 1 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is very promising for 94 GHz image radar sensors.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-0988-1
Issue No: Vol. 93, No. 1 (2017)

• A New Method Modifying Single Miller Feedforward Frequency Compensation to
Drive Large Capacitive Loads: Putting an Attenuator in the Path
Pages: 61 - 70
Abstract: Abstract A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1026-z
Issue No: Vol. 93, No. 1 (2017)

• Low leakage and high CMRR CMOS differential amplifier for biomedical
application
• Authors: Prateek Jain; Amit Mahesh Joshi
Pages: 71 - 85
Abstract: Abstract A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDD to VOUT or from VSS to VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDD to VSS directly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1027-y
Issue No: Vol. 93, No. 1 (2017)

• Four Input Single Output based third order universal filter using Four
Terminal Floating Nullor
• Authors: Huirem Tarunkumar; Ashish Ranjan; Subrahmanyam Perumalla; Nonglen Meitei Pheiroijam
Pages: 87 - 98
Abstract: Abstract This paper presents a Four Input Single Output based third order universal filter that offers all five sections of filter frequency responses with some passive components using active block named as Four Terminal Floating Nullor (FTFN). The design schematic uses two number of Four Terminal Floating Nullor (FTFN) with three numbers of resistors and capacitors each. The proposed universal filter is realised with CMOS implementation of FTFN as well as Current Feedback Operational Amplifier (CFOA) namely IC AD844 for FTFN realisation. The viability of the universal filter circuit is justified with PSPICE simulation that includes both CMOS and AD844 based realization of FTFN. Also theoretical verification is well performed for the sustainability of the proposed circuit along with experimental verification by using IC AD844.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1018-z
Issue No: Vol. 93, No. 1 (2017)

• Continuous-time analog filter with passband constant IIP3 based on
common-gate amplifier
• Authors: Marcello De Matteis
Pages: 99 - 106
Abstract: Abstract This paper presents an analog filter based on Rauch biquadratic cell. The filter exploits an improved analog stage that makes linearity performance uniform over the entire pass-band frequency region. All feedback analog filters suffer from poor linearity when the input tones frequency is in close proximity to the closed-loop poles frequency, where loop-gain reduces. This often forces an overdesign with higher current (higher power consumption) and/or higher overdrive voltages (lower dynamic range) in order to meet the linearity specifications over the whole filter pass-band region. The hereby proposed Rauch scheme resolves such a binding issue without power increasing and having the same IIP3 at low and at high frequency (up to the filter closed-loop poles frequency). Hence the linearity performance is in first approximation independent on the input tones bandwidth. In order to validate the hereby proposed idea a 4th-order 25 MHz −3 dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28 nm technology. The prototype consumes 820 µW from 1 V supply voltage and has 15  and 13 dBm IIP3 at 5 and 6 and 20 and 21 MHz input tones, respectively.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1031-2
Issue No: Vol. 93, No. 1 (2017)

• On g m -boosted follower-amplifier and its novel circuit transformation
based mid-band derivations
• Authors: S. M. Rezaul Hasan
Pages: 107 - 114
Abstract: Abstract This brief paper investigates the small-signal mid-band behavior of g m-boosted follower-amplifiers which has not been explored previously and whose analysis is not available in text-books or any other source. Both g m-boosted source follower and g m-boosted emitter follower are considered in the mid-band analysis. A novel circuit/source transformation based “pictorial” technique with progressively simplified circuit diagrams is employed for this mid-band analysis which generally eliminates the need for solving nodal or mesh equations. Final expression is often achieved by inspection of the simplified circuit without the need for circuit analysis. The paper also discusses g m-boosted BiCMOS follower amplifier using substrate PNP device in a pure CMOS process. The analysis demonstrates that the unity gain accuracy of follower-amplifier can be considerably enhanced using the g m-boosting technique without sacrificing bandwidth.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-0995-2
Issue No: Vol. 93, No. 1 (2017)

• Body controlled threshold voltage shifting variable gain current mirror
• Authors: Hassan Faraji Baghtash
Pages: 115 - 121
Abstract: Abstract A body controlled threshold voltage shifting scheme is proposed to realize a variable gain current mirror structure. The proposed structure utilizes the body terminals of MOS transistors to vary the threshold voltage and consequently the mirroring gain of current mirror structure. The application of this proposal is theoretically examined. A well-known low voltage cascode current mirror is used as a core element to realize a simple variable gain current mirror structure. The presented structure combines the transistor size switching method with body controlled threshold voltage shifting technique to achieve wide and smooth gain control range along with low power consumption. The circuits simulation results with TSMC 180 nm standard CMOS technology shows that the variable gain current mirror offers a linear-in-dB gain range of 19 dB with constant bandwidth of more than 93 MHz. The structure consumes less than 41.1 µW from 1 V power supply.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1030-3
Issue No: Vol. 93, No. 1 (2017)

• Fully digital fast transient phase-locked digital LDO-embedded-MDLL for
DVFS applications
• Authors: Muhammad Abrar Akram; In-Chul Hwang
Pages: 123 - 136
Abstract: Abstract This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (FREF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm2. At the typical VIN = 1.2 V and FREF = 37.4 MHz, the regulated range of voltage was measured to be 0.56–1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than −116 and −104 dBc/Hz, respectively, both at 1 MHz offset.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1028-x
Issue No: Vol. 93, No. 1 (2017)

• High-temperature characterisation and analysis of
leakage-current-compensated, low-power bandgap temperature sensors
• Authors: Joakim Nilsson; Johan Borg; Jonny Johansson
Pages: 137 - 147
Abstract: Abstract This paper analyses leakage current compensation techniques for low-power, bandgap temperature sensors. Experiments are conducted for circuits that compensate for collector-substrate, collector-base, body-drain and source-body leakage currents in a Brokaw bandgap sensor. The sensors are characterised and their failure modes are analysed at temperatures from 60 to $$230^{\,\circ }\hbox {C}$$ . It is found that the most appropriate compensation circuit depends on the accuracy requirements of the application and on whether a stable reference voltage is required by other parts of the circuit. Experiments show that the power consumption is dominated by leakage current at high temperatures. One type of sensor was seen to consume 260 nW at $$60 ^{\,\circ }\hbox {C}$$ , $$2.1\, \upmu \hbox {W}$$ at $$200^{\,\circ }\hbox {C}$$ and $$14\, \upmu \hbox {W}$$ at $$230^{\,\circ }\hbox {C}$$ . This work is motivated by the need to accurately monitor the temperature of power semiconductors in order to predict emerging faults in power semiconductor modules, a task for which cheap, single-chip, low-power, high-temperature, wireless bandgap temperature sensors are appropriate.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1011-6
Issue No: Vol. 93, No. 1 (2017)

• A low-power low-jitter DLL with a differential closed-loop duty cycle
corrector
• Authors: Majid Jalalifar; Gyung-Su Byun
Pages: 149 - 155
Abstract: Abstract A low-power low-jitter delay locked loop (DLL) with a first order differential closed-loop duty cycle corrector (DCC) is presented in this paper. The proposed DCC has a differential closed-loop structure that corrects the input clock duty cycle from 10 to 90%. To have a wide range DLL, a low-power voltage control delay line using wide bandwidth and large tuning range delay cells is employed. The proposed DLL has been fabricated in a 0.13 μm CMOS process technology with an active Si area of 0.11 mm2. The measured results show the DLL exhibits a lock range of 0.1–1.2 GHz while the peak-to peak jitter and rms jitter are 7.3 and 1.2 ps at 1.2 GHz, respectively. The total power dissipated by the DLL is 4.8 mW with 1.2 V supply voltage at 1.2 GHz.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-0984-5
Issue No: Vol. 93, No. 1 (2017)

• A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs
• Authors: Yo-Hao Tu; Jen-Chieh Liu; Kuo-Hsing Cheng; Chih-Hsun Hsu
Pages: 157 - 167
Abstract: Abstract This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1005-4
Issue No: Vol. 93, No. 1 (2017)

• Low power VLSI architecture design of BMC, BPSC and PC schemes
• Authors: G. Rajakumar; A. Andrew Roobert; T. S. Arun Samuel; D. Gracia Nirmala Rani
Pages: 169 - 178
Abstract: Abstract Line coding is used to tune the wave form based on the properties of the physical channel. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. The first objective of the proposed work is to design Generation and Degeneration operations of BMC, BPSC and PC techniques in a single chip. The second objective is to reduce the area and power consumption, by modifying the number of MOS devices used to design the system and by adjusting the width of the MOS devices. The proposed system is designed with 59 transistors and simulated using Cadence® 90 nm technology. This occupies 1290 µm2. Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data has equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1025-0
Issue No: Vol. 93, No. 1 (2017)

• Bulk-driven class AB fully-balanced differential difference amplifier
• Authors: Fabian Khateb; Spyridon Vlassis; Tomasz Kulej; George Souliotis
Pages: 179 - 187
Abstract: Abstract This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.
PubDate: 2017-10-01
DOI: 10.1007/s10470-017-1024-1
Issue No: Vol. 93, No. 1 (2017)

• A 0.1–1.1 GHz inductorless differential LNA with double g m -boosting
and positive feedback
• Abstract: Abstract A 0.1–1.1 GHz wideband low-noise amplifier (LNA) is proposed in this paper. The LNA is a fully differential common-gate structure. Large equivalent transconductance $$(g_m)$$ is realized by active $$g_m$$ -boost and capacitive cross-coupling. By introducing a positive feedback path, the circuit increases design freedom. It alleviates the tradeoff between input matching, gain and noise performance. The proposed LNA avoids the use of on-chip inductors to save area and cost. A prototype is implemented in standard TSMC 180-nm CMOS technology. From the measurement, the proposed LNA shows a 19 dB voltage gain with a 1 GHz 3-dB bandwidth. The minimum noise figure (NF) is 3.1 dB. The LNA achieves a return loss greater than 10 dB across the entire band and the third-order input-referred intercept (IIP3) is better than $$-\,2.9$$  dBm. The core consumes 3.8 mW from 1-V supply occupying an area of 0.03  $$\hbox {mm}^2$$ .
PubDate: 2017-09-20

• Analysis and design of low-voltage low-power high-speed double tail
current dynamic latch comparator
• Abstract: Abstract The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.
PubDate: 2017-09-19

• Enhancement of noise-suppressed speech by spectral processing implemented
in a digital signal processor
• Authors: Hajer Rahali; Zied Hajaiej
Abstract: Abstract This paper presents a noisy suppressed speech enhancement method by combining the basic spectral subtraction technique and spectral processing in the frequency domain to provide better noise suppression as well as better enhancement in the speech regions. In contrast to several previous approaches we do not try to achieve a complete removal of the noise, but instead our goal is to preserve a pre-defined amount of the original noise in the processed signal. This is accomplished by exploiting the masking properties of the human auditory system. The proposed algorithm is named PM “Proposed Method” which simulates properties of the human auditory system and applies it to the speech recognition system to enhance its robustness. The performance of the speech enhancement algorithm using the proposed masking model was compared with three other speech enhancement methods over 4 different noise types and five SNRs. The performances of the proposed approach are objectively and subjectively compared to the conventional approaches to highlight the aforementioned improvement. In this paper we discuss the design and development of a digital signal processor (DSP) implementation to achieve real-time performance of our filter. The target processor is a Texas Instruments TMS320C6713 floating point DSP.
PubDate: 2017-09-13
DOI: 10.1007/s10470-017-1042-z

JournalTOCs
School of Mathematical and Computer Sciences
Heriot-Watt University
Edinburgh, EH14 4AS, UK
Email: journaltocs@hw.ac.uk
Tel: +00 44 (0)131 4513762
Fax: +00 44 (0)131 4513327

Home (Search)
Subjects A-Z
Publishers A-Z
Customise
APIs