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Publisher: Springer-Verlag (Total: 2351 journals)

 Analog Integrated Circuits and Signal ProcessingJournal Prestige (SJR): 0.211 Citation Impact (citeScore): 1Number of Followers: 7      Hybrid journal (It can contain Open Access articles) ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030 Published by Springer-Verlag  [2351 journals]
• Introduction to the special issue on “High performance analog circuits
and design methodologies”
• Authors: Toshihiko Hamasaki; Katsu Nakamura
Pages: 193 - 194
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1333-z
Issue No: Vol. 97, No. 2 (2018)

• Three stages CMOS operational amplifier frequency compensation using
single Miller capacitor and differential feedback path
Pages: 195 - 205
Abstract: This study describes a new and simple frequency compensation for three stages amplifiers based on revered nested Miller compensation (RNMC) structure. Using only one and small compensation capacitor reduced circuit complexity and die area while shows better performance compared to RNMC. Also the proposed method is unconditional stable due to cancellation of second dominant pole by a zero. Ample simulations are performed using HSPICE and TSMC 0.18 µm CMOS technology to verify robustness of presented circuit. Simulation results show 114 dB, 6.66 MHz and 360 µW as DC gain, GBW and power consumption respectively.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1117-5
Issue No: Vol. 97, No. 2 (2018)

• Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC
• Authors: Yuki Watanabe; Hayato Narita; Hiroyuki Tsuchiya; Tatsuji Matsuura; Hao San; Masao Hotta
Pages: 207 - 214
Abstract: This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is − 0.6/+ 0.67 LSB and INL is − 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1197-2
Issue No: Vol. 97, No. 2 (2018)

• Experimental implementation of $$\Delta \Sigma$$ Δ Σ AD modulator with
dynamic analog components
• Authors: Chunhui Pan; Hao San
Pages: 215 - 223
Abstract: This paper presents an experimental prototype of 2nd-order multi-bit $$\Delta \Sigma$$ AD modulator with dynamic analog components for low power and high signal to noise and distortion (SNDR) application. The integrators in the modulator are realized by ring amplifier without static current. Multi-bit quantizer and analog adder in the feed-forward modulator is realized by a passive-adder embedded successive approximation register analog to digital converter which consists of capacitor array and a dynamic comparator. The dynamic comparator does not dissipate static power at all when a pre-amplifier is not used. Proposed modulator is fabricated in TSMC 90 nm CMOS technology. Measurement results of the modulator dynamic range is over 84 dB. Measured peak SNDR = 77.51 dB, SNR = 80.08 dB are achieved for the bandwidth of BW = 94 kHz while a sinusoid differential $$-1$$  dBFS input is sampled at 12 MS/s. The total analog power consumption of the modulator is 0.37 mW while the supply voltage is 1.1 V.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1231-4
Issue No: Vol. 97, No. 2 (2018)

• On the design of highly linear CMOS digitally programmable operational
transconductance amplifiers for low and high-frequency applications
• Authors: Mohamed B. Elamien; Soliman A. Mahmoud
Pages: 225 - 241
Abstract: This paper proposes a novel highly linear digitally programmable fully differential operational transconductance amplifier (DPOTA) circuit. Two versions of the proposed DPOTA structure are designed. The first version is optimized for high-frequency operation with current division networks designated to 3-bit control code words. On the other hand, the second version is optimized for low-frequency operation with 4-bit control code words. The third-order harmonic distortion (HD3) of the first DPOTA version remains below − 66 dB up to 0.4 V differential input voltage at 10 MHz frequency. The second DPOTA version achieved HD3 of − 70 dB with an amplitude of 20 mVp–p and at 100 Hz frequency. The proposed circuits are designed and simulated in 90 nm CMOS model, BSIM4 (level 54) under a balanced 1.2 V supply voltage.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1128-2
Issue No: Vol. 97, No. 2 (2018)

• Two-stage unbuffered CFOA based non-inverting resistive-feedback
amplifier: a study based on the description of the operational
transconductance conveyor (OTC)
• Authors: Hervé Barthélemy; Remy Vauché; Valentin Giès; Sylvain Bourdel; Jean Gaubert
Pages: 243 - 252
Abstract: A study of the non-inverting amplifier based on a two stages CMOS unbuffered current-feedback-operational-amplifier (UCFOA) is proposed in this paper. Using a small-signal equivalent circuit (macro-model) of the non-inverting amplifier, a theoretical explanation of the closed loop gain is given. The opamp phase margin and its bandwidth have been estimated from the quality factor Q of resonance and using a novel description of the UCVFOA input stage called Operational Transconductance Conveyor (OTC). The OTC description can be seen as an extension of type II second generation current conveyors. Based on the fundamental parameters of the proposed OTC, a theoretical approach given in this paper explains how to evaluate precisely the value of the UCFOA compensation capacitance. PSPICE was used to simulate both the theoretical macro-model and the CMOS configuration from a 0.35 μm typical BSIM3V3 transistor models.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1219-0
Issue No: Vol. 97, No. 2 (2018)

• Energy-efficient, fast-settling, modified nested-current-mirror,
single-stage-amplifier for high-resolution LCDs in 90-nm CMOS
• Authors: Ali Dadashi; Yngvar Berg; Omid Mirmotahari
Pages: 253 - 259
Abstract: A modified nested-current-mirror (NCM) Single-Stage amplifier, for high-performance, liquid crystal display panels, is presented in this paper. The proposed NCM is more than 8 times faster than the original NCM structure, without any extra static power consumption. Slew rate of the NCM is improved 10 times and DC-gain is also improved 6 dB, while the power consumption, gain-bandwidth product, output voltage swing range, and the phase margin of the NCM are not affected to great extent and the input-referred-noise is reduced 12%. Proposed NCMs achieve relatively higher figure of merit in comparison to previously reported NCM amplifiers and other state-of-the-art works. The significant performance improvement is obtained due to a novel slew-rate enhancer circuit. The simulation results for the designed NCM in a typical 90 nm CMOS technology confirm the predicted performance improvements.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1220-7
Issue No: Vol. 97, No. 2 (2018)

• Tensor-based methods for high-power amplifier identification and
predistortion linearization
• Authors: Zouhour Ben Ahmed
Pages: 261 - 267
Abstract: In this paper, we consider the problem of identification and predistortion of nonlinear high-power amplifier (HPA) using tensor-based methods. The HPA is modeled by a Wiener system structured as a linear time invariant system followed by memoryless nonlinearity. From a third-order Volterra kernel, we show that the linear subsystem of Wiener system can be estimated by means of the singular value decomposition algorithm. Then, the nonlinear subsystem is estimated by means least square algorithm. The identified Wiener PA model will be used to estimate a Hammerstein based predistorter using an adaptive algorithm in order to linearize the HPA. The proposed identification and predistortion methods are illustrated by means of simulation results.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1245-y
Issue No: Vol. 97, No. 2 (2018)

• Wideband transimpedance amplifier using negative capacitance and
capacitive feedback
• Authors: Preeti Singh; Maneesha Gupta; Urvashi Bansal
Pages: 269 - 279
Abstract: This paper presents a new wideband CMOS transimpedance amplifier (TIA) with low power dissipation. The negative capacitance technique is employed which reduces the parasitic capacitance. Furthermore, capacitive feedback technique is used in order to introduce pole-zero cancellation. Both these techniques, lead to bandwidth extension. Mentor Graphics Eldo simulation tool is used for simulation of the proposed TIA in TSMC 0.18 µm CMOS technology with 50 fF input photodiode capacitance. The simulated results show the − 3 dB bandwidth of 10.1 GHz which is about 8.3 GHz larger than simple TIA, transimpedance gain of 45.75 dBΩ and input current noise is 7.5 pA/√Hz with power consumption of 0.81 mW.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1246-x
Issue No: Vol. 97, No. 2 (2018)

• OTRA, its implementations and applications: a state-of-the-art review
• Authors: Abdhesh K. Singh; Raj Senani; Ashish Gupta
Pages: 281 - 311
Abstract: During the last three decades, a large number of new analog circuit building blocks have emerged beyond the well-known operational amplifier, operational transconductance amplifier, Current Conveyors and Current feedback operational amplifier. Among the new building blocks, the operational transresistance amplifier (OTRA) has received considerable attention in the literature. This paper presents a state-of-the-art review of the OTRAs, their bipolar and CMOS implementations and applications in linear and nonlinear analog signal processing/generation along with a comprehensive list of references covering the period from 1992 till date.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1311-5
Issue No: Vol. 97, No. 2 (2018)

• Design of high-linearity 75–90 GHz CMOS down-conversion mixer
• Authors: Dongfang Pan; Zongming Duan; Lu Huang; Yan Wang; Yang Zhou; Bowen Wu; Liguo Sun
Pages: 313 - 322
Abstract: This paper presents a 75–90 GHz down-conversion mixer applied in automotive radar, which is characterized with high linearity, low local oscillator (LO) drive as well as high conversion gain (CG) using TSMC 65-nm CMOS general-purpose technology. The good linearity and isolation of mixer are required for automotive radar to cover short-middle-far range detection. The mixer includes an enhanced double-balanced Gilbert-cell core with series peaking transmission line and source degeneration technique for improving linearity and CG, two on-chip baluns and intermediate frequency (IF) buffer for IF test. Besides, to make the design more accurate and efficient, the modeling and design of millimeter-wave (mm-wave) passive devices are introduced. The mixer consumes 12 mW under 1.5 V. The input 1 dB compression point (P1dB) is 2.5 dBm as well as IIP3 of 13.2 dBm at 80 GHz. High performances are achieved with the CG of 5 dB at 76 GHz with LO power of 0 dBm for frequencies of 75–90 GHz which covers the application of automotive radar frequency band (76–81 GHz) and LO-RF isolation of 33–37 dB for frequencies of 60–90 GHz. The area of the mixer is 0.14 mm2, with PADs included.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1247-9
Issue No: Vol. 97, No. 2 (2018)

• Tunable LNA filter design using coupled-inductor Q-enhancement
• Authors: Michel Al Khoury; Bernard Jarry; Bruno Barelaud; Julien Lintignat
Pages: 323 - 332
Abstract: A tunable LNA filter using Q-enhanced inductors is designed in 0.25 μm BiCMOS Qubic4x technology. The design employs the inductor degenerated LNA, acting as a transconductance which converts the input voltage to output current which drives the second-order Q-enhanced filter. The filter also uses a special technique based on coupled-inductor negative resistance generator to make the quality factor and the center frequency tunable. The overall gain of the LNA filter is about 19.5 dB and the minimum noise figure is 6.4 dB. The center frequency is 942.5 MHz with a 42 MHz (3 dB) bandwidth.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1248-8
Issue No: Vol. 97, No. 2 (2018)

• A highly extended high-efficiency range Doherty power amplifier for high
PAPR communication signals
Pages: 333 - 341
Abstract: In this paper, design, simulation and fabrication of a new highly extended high-efficiency range Doherty power amplifier (DPA) for high peak to average power ratio (PAPR) communication signals were presented with a main and only a single auxiliary amplifier. In order to extend the output high-efficiency range, it employed non-equal cells as main and auxiliary amplifiers in the complex combining load (CCL) methodology. As a new method, a new design parameter ( $$\gamma$$ ) was added to the conventional complex combining load method. The effect of the new added design parameter on extension of output back-off (OBO) were analyzed and formulated. Also, to verify the proposed methodology, a DPA with 12 dB of OBO was designed, simulated and fabricated for WCDMA applications. Large signal continuous wave measurement results show the power gain of 11 dB with the drain efficiency of 53% at 12 dB of OBO. Two-tone test exhibits the third-order intermodulation distortion lower than − 34 dBc. Modulated wave simulations show over 51% of average drain efficiency and lower than − 31 dBc of adjacent channel leakage power ratio at output power level of 31.5 dBm.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1280-8
Issue No: Vol. 97, No. 2 (2018)

• A 90-nm CMOS 800 MHz 2 $$\times$$ × VDD output buffer with leakage
• Authors: Chua-Chin Wang; Tsung-Yi Tsai; Wei Lin
Pages: 343 - 350
Abstract: This work presents a 800 MHz 2 $$\times$$ VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 $$\times$$ 0.439 mm $$^2$$ , and the power consumption is 68.9/98.5 ( $$\upmu$$ W/MHz) at 450/800 MHz, respectively.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1285-3
Issue No: Vol. 97, No. 2 (2018)

• G m -boosted current-reuse inductive-peaking common source LNA for
3.1–10.6 GHz UWB wireless applications in 32 nm CMOS
• Authors: Vikram Singh; Sandeep Kumar Arya; Manoj Kumar
Pages: 351 - 363
Abstract: A low power, low noise amplifier (LNA) for 3.1–10.6 GHz ultra-wideband (UWB) wireless applications is reported in this paper. The proposed LNA is designed using common source (CS) current-reused architecture. Flat and high power gain (S21) with constant noise figure (NF) is achieved using series inductive peaking between CS primary stage and the current reused second stage. Input–output matching networks have been used to achieve acceptable values of input reflection coefficient (S11) and output reflection coefficient (S22) for the complete UWB frequency range. The use of inductive peaking with current reused architecture enhances the overall performance of proposed ultra-wideband LNA. The LNA is analyzed and designed using 32 nm CMOS process. It has a constant NF of 2.7 dB, a high and flat S21 of 23.8 ± 0.7 dB with high reverse isolation (S12) of < − 37.3 dB. The proposed LNA provides acceptable results for S11 and S22 parameters with values less than − 7.5 and − 11.0 dB respectively, for the UWB frequency range of 3.1–10.6 GHz. The proposed LNA provides 1-dB compression point (P1dB) of − 20 dBm and third order intercept point (IIP3) of − 10 dBm. The power consumed by the reported LNA is only 8.05 mW for a 0.7 V power supply.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1290-6
Issue No: Vol. 97, No. 2 (2018)

• A novel low power flip-flop design using footless scheme
• Authors: Jin-Fa Lin; Ming-Yan Tsai; Ching-Sheng Chang; Yu-Ming Tsai
Pages: 365 - 370
Abstract: A low power true-single-phase clocking flip-flop (FF) design by using FootLess scheme named FLFF design targeting low VDD and low power operations is proposed. It is adapted from a recently presented FF design and achieves circuit simplification by using hybrid logic style. The optimization measure leads to a new design featuring better both power and speed performances. Based on the simulation results, the proposed design outperforms the conventional transmission gate flip-flop (TGFF) by 84% in energy. An 8-bit Johnson-counter consisting of the proposed FF design is developed and implemented. For the target 250 MHz working frequency, the proposed design achieves over 48.3% power saving with 14.6% area reducing.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1327-x
Issue No: Vol. 97, No. 2 (2018)

• Low power analog comb filter for biomedical applications
• Authors: Sajal K. Paul; Chandan Kumar Choubey; Gaurav Tiwari
Pages: 371 - 386
Abstract: An analog topology is proposed to implement a comb filter for removal of power-line interference from various low-amplitude biomedical signals. In this proposed methodology, an n-number of all-pass filters (APFs) and an adder circuit are used to suppress n-number of frequencies. All the APFs as well as the adder circuit are designed using a current conveyor to utilize the various properties of the current-mode circuits. The active and passive components used to design the comb filter include second-generation current conveyor (CCII±), resistor, and capacitor. The circuit is designed for n = 4 to remove the power-line frequency of 50 Hz, and its three odd harmonics such as 150 Hz, 250 Hz, and 350 Hz. A PSPICE simulation is done to verify the performance of the proposed circuit. In simulation, all CCII± are designed using macro model of commercially-available current feedback operational amplifier integrated circuit (IC) AD844 as well as dynamic threshold voltage metal oxide semiconductor technology. The proposed circuit is also implemented also using commercially available IC AD844 on breadboard for n = 3. The output result on digital storage oscilloscope confirm the effectiveness of the proposed comb filter circuit in removing the power line interference i.e. the power-line frequency and its odd harmonics.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1329-8
Issue No: Vol. 97, No. 2 (2018)

• A blind digital background calibration for all-digital VCO-based ADC
• Authors: Yuke Zhang; Kamal El-Sankary; Jianjun Zhou
Pages: 387 - 394
Abstract: A new blind digital background calibration for nonlinearity compensation of voltage-controlled oscillator based analog-to-digital converter is proposed in this letter. The proposed technique is blind and does not require the injection of an additional calibration signal. It takes advantage of the fact that the in-band and the out-of-band distortions have the same origin. By cancelling the out-of-band distortions, in-band distortions can also be removed. This new technique draws support from the orthogonal polynomials least mean square (LMS) algorithm to improve the computational efficiency. Finally, the proposed technique improves the signal-to-noise ratio by more than 40 dB after convergence of the LMS algorithm.
PubDate: 2018-11-01
DOI: 10.1007/s10470-018-1340-0
Issue No: Vol. 97, No. 2 (2018)

• A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC
• Authors: Masood Teymouri; Jafar Sobhi
Abstract: This paper presents a full high definition 1920 × 1080 pixel, 120 frames/s CMOS image sensor with two-step single-slope (TS-SS) ADC. The column-parallel TS-SS ADC and binary subtractor are used to convert photodiode voltage to the final 10-bit digital data. Therefore, there is no need for the pixel readout, noise suppression or comparator offset cancellation circuits to be used in the columns. A new ramp signal generator is proposed to generate 32 concurrent and identical ramp signals. TS-SS ADC improves the conversion speed while reducing the power consumption level as well. The proposed image sensor has been designed using TSMC 0.18 μm 1-poly 4-metal standard process. The simulation results show that the total comparator referred noise to the FD node in 1 Hz–100 MHz range is 0.574 mV and, also the total power consumption is about 100 mW.
PubDate: 2018-10-17
DOI: 10.1007/s10470-018-1349-4

• A 24–28 GHz high-stability CMOS power amplifier using
common-gate-shorting (CGS) technique with 17.5 dBm $${\hbox {P}}_{sat}$$
P sat and 16.3% PAE for 5G millimeter-wave applications
• Authors: Chunshen Jiang; Runxi Zhang; Chunqi Shi
Abstract: This paper presents a 24–28 GHz high-stability millimeter-wave power amplifier (PA) implemented in low-cost $$0.13\, \upmu \hbox {m}$$ CMOS process. The PA consists of two cascode stages with passive transformer-based input and output baluns. The common-gate-shorting technique is proposed for high-stability and high-gain millimeter-wave cascode stage. To realize this technique, an interdigited powercell structure is adopted for MOS layout optimization. In order to improve $$\hbox {P}_{out}$$ and PAE, an inter-stage inductor is introduced. The proposed PA achieves a PAE over 16.3% with a saturated output power of 17.5 dBm. The maximum gain is 21.2 dB at 26 GHz.
PubDate: 2018-10-15
DOI: 10.1007/s10470-018-1350-y

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