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Publisher: Springer-Verlag (Total: 2350 journals)

 Analog Integrated Circuits and Signal Processing   [SJR: 0.21]   [H-I: 37]   [7 followers]  Follow         Hybrid journal (It can contain Open Access articles)    ISSN (Print) 1573-1979 - ISSN (Online) 0925-1030    Published by Springer-Verlag  [2350 journals]
• An OTA gain enhancement technique for low power biomedical applications
• Authors: Rajasekhar Nagulapalli; Khaled Hayatleh; Steve Barker; Saddam Zourob; Nabil Yassine
Pages: 387 - 394
Abstract: The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of − 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um2 silicon area.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1148-y
Issue No: Vol. 95, No. 3 (2018)

• A robust high-efficiency cross-coupled charge pump circuit without
blocking transistors
• Authors: Minglin Ma; Xinglong Cai; Yichuang Sun; Nike George
Pages: 395 - 401
Abstract: A fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1149-x
Issue No: Vol. 95, No. 3 (2018)

• Increasing signal to noise ratio and minimizing artefacts in biomedical
instrumentation systems
• Authors: Saddam Zourob; Khaled Hayatleh; Steve Barker; Rajasekhar Nagulapalli; Nabil Yassine; Roger Ramsbottom; John Lidgey
Pages: 403 - 408
Abstract: Capturing a near-perfect, artefact free signal is an ideal of biomedicine. However, this depends on the removal of different types of artefact, all of which can be considered unwanted noise on the desired signal. Failure to remove artefacts could lead to a clinical misinterpretation of the results. All medical equipment such as electrocardiogram systems which use electrodes attached to patients suffer from artefacts, with effects ranging from minor blurring to significant distortion of the output signal(s). For this reason, it is important to identify how artefacts can influence the output signal. In this paper, we propose a new technique to detect and minimise movement artefacts using strain gauges embedded into the electrodes.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1150-4
Issue No: Vol. 95, No. 3 (2018)

• Simulation of driver fatigue monitoring via blink rate detection, using
65 nm CMOS technology
• Authors: Nabil Yassine; Steve Barker; Khaled Hayatleh; Bhaskar Choubey; Rajasekhar Nagulapalli
Pages: 409 - 414
Abstract: This paper proposes a system to detect and measure blink rate to determine fatigue levels. The method involved analysing specific frames to determine that a blink occurred, and then monitoring the time between successive blinks. The program was simulated in python using a Raspberry Pi Zero and a standard USB camera. For the blink rate detection block, a gate level schematic was implemented in Cadence software using 65 nm CMOS technology. The design was based around an asynchronous 6-bit based edge counter which was designed using D-flip-flops. The simulation calculated the average blink rate and compared this to the most recent blink rate. The outcome would determine if an alarm signal should be sent to the alarm. The system consumed 130 μA from a 1.2 V power supply.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1151-3
Issue No: Vol. 95, No. 3 (2018)

• An analysis of vehicle-to-infrastructure communications for non-signalised
intersection control under mixed driving behaviour
• Authors: Gokhan Budan; Khaled Hayatleh; Denise Morrey; Peter Ball; Philip Shadbolt
Pages: 415 - 422
Abstract: Intersection control has an important role in the management of urban traffic to ensure safety, high traffic flow and to prevent congestion. Recently, a growing body of literature has been reported on the theme of non-signalised intersection control in which traffic lights are replaced with intelligent road side units. Data from several studies suggest that non-signalised control could reduce vehicle delays and fuel consumption significantly whilst ensuring safety. However, there is little published data on the impact of the mixed driving behaviour with human-driven vehicles and autonomous vehicles. This paper investigates the emerging role of connectivity and vehicle autonomy in the context of traffic control under the mixed driving behaviour scenario. The concepts of vehicle-to-infrastructure (V2I) communications and multi-agent systems are central to achieving a robust and reliable traffic-light-free intersection control. Comprehensive computer simulation results on a four-way intersection indicate over 96% reduced average vehicle delay and 37% less fuel consumption with the non-signalised control solution compared to the traffic light control. The outcome of this study offers some important insights into enabling cooperation between vehicles and traffic infrastructure via V2I communications, in order to make more efficient real-time decisions about traffic conditions, whilst ensuring a higher degree of safety.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1152-2
Issue No: Vol. 95, No. 3 (2018)

• Fully automated lung segmentation from chest radiographs using SLICO
superpixels
• Authors: Bilal Yassine; Paul Taylor; Al Story
Pages: 423 - 428
Abstract: This project aims to create a computer-aided diagnosis (CAD) system that can be used to identify tuberculosis (TB) from chest radiographs (CXRs) and, in particular, to observe the progress of the disease where patients have had multiple images over a period of time. Such a CAD tool, if sufficiently automated could run in the background checking every CXR taken, regardless of whether the patient is a suspected carrier of TB. This paper outlines the first phase of the project: segmenting the lung region from a CXR. This is a challenge because of the variation in the appearance of the lung in different patients and even in images of the same patient.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1153-1
Issue No: Vol. 95, No. 3 (2018)

• Neuron inspired data encoding memristive multi-level memory cell
• Authors: Aidana Irmanova; Alex Pappachen James
Pages: 429 - 434
Abstract: Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1155-z
Issue No: Vol. 95, No. 3 (2018)

• Inverse eigenvalue sensing with corner coupled square plate MEMS
resonators array
• Authors: Guowei Tao; Bhaskar Choubey
Pages: 447 - 455
Abstract: Monitoring the collective behaviour of coupled micro/nano resonators array provides a distinct opportunity for high resolution multi-function sensing. We report an inverse eigenvalue analysis based sensing approach for large array of coupled micro/nano resonators. A new characterization algorithm is proposed to precisely extract the system matrix of those multiplexed sensors with reduced algorithmic complexity and below 1% relative error. The method has been verified experimentally using five corner coupled square plate MEMS resonators with a natural frequency close to 0.85 MHz. The method is also capable of characterizing the fabrication process and important sensor parameters such as the spring constant and coupling ratio.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1160-2
Issue No: Vol. 95, No. 3 (2018)

• Feature extraction without learning in an analog spatial pooler
memristive-CMOS circuit design of hierarchical temporal memory
• Authors: Olga Krestinskaya; Alex Pappachen James
Pages: 457 - 465
Abstract: Hierarchical temporal memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1161-1
Issue No: Vol. 95, No. 3 (2018)

• A memristor-based long short term memory circuit
• Authors: Kamilya Smagulova; Olga Krestinskaya; Alex Pappachen James
Pages: 467 - 472
Abstract: Long-short term memory (LSTM) is a cognitive architecture that aims to mimic the sequence temporal memory processes in human brain. The state and time-dependent based processing of events is essential to enable contextual processing in several applications such as natural language processing, speech recognition and machine translations. There are many different variants of LSTM and almost all of them are software based. The hardware implementation of LSTM remains as an open problem. In this work, we propose a hardware implementation of LSTM system using memristors. Memristor has proved to mimic behavior of a biological synapse and has promising properties such as smaller size and absence of current leakage among others, making it a suitable element for designing LSTM functions. Sigmoid and hyperbolic tangent functions hardware realization can be performed by using a CMOS-memristor threshold logic circuit. These ideas can be extended for a practical application of implementing sequence learning in real-time sensory processing data.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1180-y
Issue No: Vol. 95, No. 3 (2018)

• A fully integrated 4-channel GMR biochip for biomedical detection
applications
• Authors: Cheng Zhu; Lei Zhang; Xizeng Shi; He Qian
Pages: 513 - 521
Abstract: This paper proposed a fully integrated 4-channel GMR biochip for biomedical detection assays, including the acquisition analog frontend for small signal extraction, 180° phase shifter, resistor ladder and control circuits for carrier cancellation, and amplifiers. Besides, the overall system was evaluated comprehensively by experiment, and the output noise is as low as $$321.7\mathrm {nV/\sqrt{Hz}},$$ which is lower than the signal produced by one single 500nm magnetic particle during the detection.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1154-0
Issue No: Vol. 95, No. 3 (2018)

• Adaptive current-threshold detector for an adaptive on-time Buck converter
• Authors: Qinqin Li; Xinquan Lai; Longjie Zhong
Pages: 541 - 549
Abstract: The adaptive on-time control technique has been tremendously utilized in DC–DC converters for its fast transient response, easier design and high efficiency at light load. In some applications the output voltage ripple of DC–DC converters has to be maintained within an acceptable level to achieve superior performance, which depends largely on the load current for adaptive on-time buck converters when operating in discontinuous conduction mode. This paper proposes an adaptive current-threshold detection method for reducing the output voltage ripple. An actual detector circuit is presented to implement the method. This circuit monitors the relationship between the peak inductor current and the load current at light load. Then it outputs a logic signal which controls the turn-on time of the main power MOSFET and hence the peak inductor current. Therefore, the magnitude of the output voltage ripple is controlled. The current-threshold detection method has been verified in an adaptive on-time buck converter by simulation and experimental results. The proposed method can also be used in other constant on-time converters.
PubDate: 2018-06-01
DOI: 10.1007/s10470-018-1140-6
Issue No: Vol. 95, No. 3 (2018)

• Harmonic suppression in short-circuited stub bandpass filter by means of a
new miniaturized bandstop filter
• Authors: Tahereh Beiki; Mirshahram Hosseinipanah
Abstract: In this article, a conventional short-circuited stub bandpass filter cascaded with a new miniaturized bandstop filter is presented which results in suppression of the spurious signals. The crown bandstop filter is proposed and designed using transmission line model. The combination of a crown bandstop filter, a complementary spiral resonator and a spurline is used to obtain the proposed bandstop filter with wide stopband and high rejection level. The proposed bandstop filter size is 0.31λg* 0.31λg and has a wide 3-dB stop bandwidth of 3.5 GHz. The prototype of the harmonic suppressed short-circuited stub bandpass filter is fabricated and measured. The measured upper stopband is better than 30 dB up to 3.5f0. The measured results are in good agreement with corresponding simulation results.
PubDate: 2018-06-09
DOI: 10.1007/s10470-018-1230-5

• Low power SAR ADC switching without the need of precise second reference
• Abstract: In this paper a simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the proposed method does not require the intermediate voltage to be accurate. The implementation of digital control and an intermediate voltage-level generator is considered. To evaluate the reduction in switching energy compared to the conventional monotonic switching procedure, the behavioral model of a 10-bit ADC was examined. The additional digital logic, voltage generator, and capacitive DAC were modeled at a transistor level using a 65 nm STM design kit. Simulation results and the subsequent power efficiency gains are presented.
PubDate: 2018-06-07
DOI: 10.1007/s10470-018-1225-2

• Design of a fA wide dynamic range ADC for current sensing
• Abstract: Current sensing is important in various applications. The Utopia 2 Application Specific Integrated Circuit (ASIC) was developed in AMS 0.35 $$\upmu \hbox {m}$$ technology for radiation monitoring based on ionization chambers. The ASIC is able to measure current equal to 1 femtoampere (fA) after active leakage current compensation. The compensation is achieved with a second dummy compensating channel that is matched to the measuring channel. The ASIC was also designed to cope with input currents that span over nine decades of dynamic range. The analog to digital conversion is performed with charge balancing and counting. The maximum current that is equal to 5 $$\upmu \hbox {A}$$ can be measured after the introduction of a second range. The system has been characterized at a certified laboratory and is able to sense currents from 1 fA up to 5 $$\upmu \hbox {A}$$ .
PubDate: 2018-06-06
DOI: 10.1007/s10470-018-1224-3

• Two-stage unbuffered CFOA based non-inverting resistive-feedback
amplifier: a study based on the description of the operational
transconductance conveyor (OTC)
• Authors: Hervé Barthélemy; Remy Vauché; Valentin Giès; Sylvain Bourdel; Jean Gaubert
Abstract: A study of the non-inverting amplifier based on a two stages CMOS unbuffered current-feedback-operational-amplifier (UCFOA) is proposed in this paper. Using a small-signal equivalent circuit (macro-model) of the non-inverting amplifier, a theoretical explanation of the closed loop gain is given. The opamp phase margin and its bandwidth have been estimated from the quality factor Q of resonance and using a novel description of the UCVFOA input stage called Operational Transconductance Conveyor (OTC). The OTC description can be seen as an extension of type II second generation current conveyors. Based on the fundamental parameters of the proposed OTC, a theoretical approach given in this paper explains how to evaluate precisely the value of the UCFOA compensation capacitance. PSPICE was used to simulate both the theoretical macro-model and the CMOS configuration from a 0.35 μm typical BSIM3V3 transistor models.
PubDate: 2018-06-05
DOI: 10.1007/s10470-018-1219-0

• An accurate time-to-digital converter based on a self-timed ring
oscillator for on-the-fly time measurement
• Authors: Assia El-Hadbi; Abdelkarim Cherkaoui; Oussama Elissati; Jean Simatic; Laurent Fesquet
Abstract: This paper proposes a new architecture of a time-to-digital converter (TDC) based on a self-timed ring (STR) oscillator with sub-gate delay resolution. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Exploiting the phase difference between events propagating in the same STR without collision, this TDC benefit from a uniform phase distribution. Thus, under certain conditions, a regular time base can be generated and a compact readout algorithm can be applied. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. As a proof-of-concept, an STR-based TDC with only 9-stages has been simulated using 28 nm FDSOI technology. A time resolution of 8.9 ps has been achieved. Without using calibration, the measured DNL and INL are 0.44 and 0.40 LSB, respectively. Simulation results point out the advantage of this TDC in terms of measurement accuracy and state the limit of the on-the-fly measurement according to the dependency between the jitter and the time resolution.
PubDate: 2018-06-05
DOI: 10.1007/s10470-018-1223-4

• SC amplifier and SC integrator with enhanced immunity to capacitor
mismatch
• Authors: Chi-Chang Lu; Hou-Ming Chen
Abstract: Novel switched-capacitor amplifier and integrator with enhanced immunity to capacitor mismatch are presented. Both circuits are based on a capacitor mismatch compensation scheme that the amount of the transferred charge is only dependent on one of the capacitors, instead of the ratio of the two capacitors. The proposed multiply-by-two amplifier requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error caused by capacitor mismatch and provides better power efficiency. Furthermore, the proposed integrator with an accurate gain of one is insensitive to capacitor-mismatch and the input offset voltage of the opamp is removed completely. Finally, Monte-Carlo simulation results are presented to confirm the feasibility of these new techniques, demonstrating its suitability in high-resolution pipelined ADC or sigma-delta modulator.
PubDate: 2018-06-04
DOI: 10.1007/s10470-018-1212-7

• Oxford circuits and systems conference
• Authors: Bhaskar Choubey; Khaled Hayatleh; Alex Pappachen James
PubDate: 2018-04-25
DOI: 10.1007/s10470-018-1193-6

• A compensation scheme for non-ideal circuit effects in biomedical
impedance sensor
• Authors: Yan Hong; Wang Ling Goh; Yong Wang
Abstract: The accuracy of an I/Q based biomedical impedance sensing sensor (IQBIS) suffers significantly from the PVT effects of the analog front-end, such as the amplitude errors of the stimulation signals, gain mismatches, amplitude and phase imbalances of in-phase (I) and quadrature (Q) signals, etc. These practical effects will severely impede the system performance if handled improperly. In this paper, the degradations of sensing performance by such imperfections are mathematically analyzed and quantified. Following theoretical studies, a digitally controlled correction approach is proposed to finely alleviate these impairments. The performance of the proposed scheme had been verified using Simulink and MATLAB. With the proposed error correction scheme, the accuracy is improved by at least 17 times compared to that of the typical IQBIS, for both real and imaginary values of impedance. Thus, the proposed method is very useful for IQBIS, in resisting degradation in sensing accuracies due to the process-voltage-temperature (PVT) effects.
PubDate: 2018-04-25
DOI: 10.1007/s10470-018-1182-9

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