Abstract: Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters. Seven different carry select adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance. PubDate: Wed, 27 May 2015 12:48:59 +000
Abstract: Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, , temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately. PubDate: Tue, 24 Feb 2015 14:06:10 +000
Abstract: A new proposed compensation driver circuit of flat-panel display (FPD) based on organic light emitting diodes (OLEDs) and on poly-crystalline silicon thin-film transistors (poly-Si TFTs) is presented. This driver circuit is developed for an active-matrix organic light-emitting-diode (AMOLED) display and its efficiency is verified compared with the conventional configuration with 2 TFTs. According to results, this circuit is suitable to achieve acceptable level for power consumption, high contrast, maximum gray levels, and better brightness. And, to show this, a stable driving scheme is developed for circuit with much compensation such as against the data degradation, the threshold voltage dispersions of TFT drive, and suppression of TFT leakage current effect. PubDate: Tue, 10 Feb 2015 07:33:33 +000
Abstract: This paper presents multiphase sinusoidal oscillators (MSOs) using operational transresistance amplifier (OTRA) based all pass networks. Both even and odd phase oscillations of equal amplitudes which are equally spaced in phase can be produced using single all pass section per phase. The proposed MSOs provide voltage output and can readily be used for driving voltage input circuits without increasing component count. The effect of nonideality of OTRA on the circuit performance is also analysed. The functionality of the proposed circuit is verified through PSPICE simulations. PubDate: Wed, 21 Jan 2015 08:37:55 +000
Abstract: A wearable smart locator band is an electronic device which can be worn on the wrist of the children to monitor and keep an eye on them. As the number of mishaps with children is increasing, it is a must to keep them safe. This also helps reducing crime rates. The research study proposed the development of a wearable smart locator band that helps keeping track of kids. The developed device includes an AVR microcontroller (ATmega8515), global positioning system (GPS), global system for mobile (GSM), and switching unit and the monitoring unit includes Android mobile device in parent’s hand with web based Android application as well as location indicated on a Google Map. This development is very useful for senior people and individuals suffering from memory diseases. This device, hence, behaves as a communication interface between wearer and caregiver. PubDate: Thu, 15 Jan 2015 13:30:39 +000
Abstract: Bioimpedance measurement is gaining importance in wide field of bioresearch and biomedical systems due to its noninvasive nature. Noninvasive measurement method is very important to decrease infection and physical injuries which result due to invasive measurement. This paper presents basic principle of bioimpedance along with its application for blood glucose analysis and effect of frequency on impedance measurement. Input from bioimpedance sensor is given to amplifier and signal conditioner AD5933. AD5933 is then interfaced with microcontroller LPC1768 using I2C bus for displaying reading on LCD. Results can also be stored in database using UART interface of LPC1768. PubDate: Sun, 28 Dec 2014 00:10:09 +000
Abstract: This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage. PubDate: Tue, 23 Dec 2014 10:53:45 +000
Abstract: Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain the effective number of bit 9.55 in 100 KS/s sampling rate. PubDate: Sun, 21 Dec 2014 00:10:05 +000
Abstract: Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog signals, optimized for the communication medium, to the optimal on-chip signal representation, the digital one, for the IC medium. The signals in the AMS part itself are consequently not optimally matched to the IC medium. To further shift the frontiers of AMS design, a matching-driven design approach is crucial for AMS. Four levels will be addressed: technology-driven, states-driven, redundancy-driven, and nature-driven design. This is done based on an analysis of the various classes of AMS signals and their specific properties, seen from the angle of redundancy. This generic, but abstract way of looking at the design process will be substantiated with many specific examples. PubDate: Tue, 16 Dec 2014 08:03:34 +000
Abstract: The principal objective of this paper is to demonstrate the capability of high speed measurement and acquisition equipment design and build in the laboratory at a very low cost. The presented architecture employees highly integrated market components eliminating thus the complexity of the hardware and software stack. The key element of the proposed system is a Hi-Speed USB to Serial/FIFO development module that is provided with full software and driver support for most popular operating systems. This module takes over every single task needed to get the data from the A/D to the user software gluelessly and transparently, solving this way the most difficult problem in data acquisition systems which is the fast and reliable communication with a host computer. Other ideas tested and included in this document offer Hall Effect measuring solutions using some excellent features and very low cost ICs widely available on the market today. PubDate: Sun, 16 Nov 2014 09:34:06 +000
Abstract: In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA. PubDate: Mon, 22 Sep 2014 05:56:17 +000
Abstract: Since Moore’s law driven scaling of planar MOSFETsfaces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owingto the presence of multiple (two/three) gates, FinFETs/TrigateFETs are able to tackle short-channel effects (SCEs) better thanconventional planar MOSFETs at deeply scaled technology nodesand thus enable continued transistor scaling. In this paper, wereview research on FinFETs from the bottommost device levelto the topmost architecture level. We survey different types ofFinFETs, various possible FinFET asymmetries and their impact,and novel logic-level and architecture-level tradeoffs offered byFinFETs. We also review analysis and optimization tools thatare available for characterizing FinFET devices, circuits, andarchitectures. PubDate: Sun, 07 Sep 2014 12:07:09 +000
Abstract: A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW. PubDate: Wed, 27 Aug 2014 08:10:45 +000
Abstract: Image recognition with occlusion is one of the popular problems in pattern recognition. This paper partitions the images into some modules in two layers and the sparsity difference is used to evaluate the occluded modules. The final identification is processed on the unoccluded modules by sparse representation. Firstly, we partition the images into four blocks and sparse representation is performed on each block, so the sparsity of each block can be obtained; secondly, each block is partitioned again into two modules. Sparsity of each small module is calculated as the first step. Finally, the sparsity difference of small module with the corresponding block is used to detect the occluded modules; in this paper, the small modules with negative sparsity differences are considered as occluded modules. The identification is performed on the selected unoccluded modules by sparse representation. Experiments on the AR and Yale B database verify the robustness and effectiveness of the proposed method. PubDate: Mon, 18 Aug 2014 08:20:38 +000
Abstract: Medium-range inductive wireless power transmission systems allow a sufficient power transfer without requiring close proximity between a primary coil and a secondary coil. We briefly investigate the range of a typical system and its radiated emission, from the perspectives of electromagnetic compatibility (EMC) and human exposure requirements. We then discuss the applicable legislation in the European Union, the main question being the applicability of the R&TTE or radio equipment directives. Our conclusion is that this applicability depends on multiple parameters, among which is the presence of a self-tuning capability or of a transmitter control based on telemetry. PubDate: Thu, 10 Jul 2014 19:39:57 +000
Abstract: Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field. PubDate: Tue, 29 Apr 2014 14:20:47 +000
Abstract: InAs/(In,Ga)Sb type-II strained layer superlattices (T2SLs) have made significant progress since they were first proposed as an infrared (IR) sensing material more than three decades ago. Numerous theoretically predicted advantages that T2SL offers over present-day detection technologies, heterojunction engineering capabilities, and technological preferences make T2SL technology promising candidate for the realization of high performance IR imagers. Despite concentrated efforts of many research groups, the T2SLs have not revealed full potential yet. This paper attempts to provide a comprehensive review of the current status of T2SL detectors and discusses origins of T2SL device performance degradation, in particular, surface and bulk dark-current components. Various approaches of dark current reduction with their pros and cons are presented. PubDate: Thu, 10 Apr 2014 14:10:25 +000
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