Abstract: To quickly destroy electronic devices and ensure information security, a destruction mechanism of transient electronic devices was designed in this paper. By placing the Ni-Cr film resistance and the energetic material between the chip and the package and heating the resistance by an electric current, the energetic material expanded and the chip cracked. The information on the chip was destroyed. The author simulated the temperature distribution and stress of the power-on structure in different sizes by ANSYS software. The simulation results indicate that the chip cracks within 50 ms under the trigger current of 0.5 A when a circular groove with an area of 1 mm2 and depth of 0.1 mm is filled with an expansion material with an expansion coefficient of 10−5°C−1. Then, the author prepared a sample for experimental verification. Experimental results show that the sample chip quickly cracks and fails within 10 ms under the trigger current of 1 A. The simulation and experimental results confirm the feasibility of the structure in quick destruction, which lays the foundation for developing instantaneous-failure integrated circuit products to meet information security applications. PubDate: Thu, 31 Dec 2020 13:05:00 +000
Abstract: Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces. PubDate: Thu, 03 Dec 2020 05:20:00 +000
Abstract: Wireless power transfer (WPT) is one solution to realize long flight times and accommodate various missions of micro-uncrewed aerial vehicles (MAVs). Reducing the constraint of power transmission distance and realizing high beam efficiency are possible because of the high directivity of WPT using millimeter wave (MMW) methods. Nevertheless, no report of the relevant literature describes an investigation of sending power to an MAV using MMW because MMW rectennas have low efficiency. The purpose of our study is to conduct fundamental research of a high-efficiency and high-power rectenna at 94 GHz aimed at MAV application using MMW. As described herein, we developed and evaluated a 100-mW-class single-diode rectifier at 94 GHz with a finline of a waveguide (WG) to a microstrip-line (MSL) transducer. With the optimum load of 150 Ω at input power of 128 mW, the output DC power and rectifying efficiency were obtained respectively as 41.7 mW and 32.5%. By comparison to an earlier study, measurement of 94 GHz rectifiers under high power input becomes more accurate through this study. PubDate: Fri, 21 Aug 2020 17:35:01 +000
Abstract: The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively. PubDate: Mon, 30 Mar 2020 08:20:00 +000
Abstract: An ease of four-port dual-mode diplexer with high signal isolation is presented. A compact dual-mode diplexer with high signal isolation between the Rx and Tx modules is achievable by only using one resonator filter topology. Two back-to-back dual-mode diplexers have a 180° phase shift in one branch. The high isolation can be achieved by amplitude and phase cancellation technique. The delayed transmission line can be easily achieved by the phase shifter. The simulated and measured four-port dual-mode diplexers are designed at the centre frequency of Rx/Tx at 1.95 GHz and 2.14 GHz, respectively. The measured results of Rx/Tx dual-mode diplexer devices are presented with 47.1 dB Rx/Tx isolation. This four-port dual-mode diplexer achieves the isolation (S32) of more than 24.1 dB when compared with the conventional three-port dual-mode diplexer structure. PubDate: Mon, 10 Feb 2020 08:50:00 +000
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