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Journal Cover
Journal of VLSI Design Tools & Technology
Number of Followers: 5  
  Full-text available via subscription Subscription journal
ISSN (Print) 2249-474X
Published by STM Journals Homepage  [36 journals]
  • Design and Implementation of an Efficient Ternary Control Unit
    • Authors: SS Narkhede, BS Chaudhari, GK Kharate
      Abstract: Multi-valued logic (MVL) is emerging as a thrust area of research due to several advantages offered by them over the conventional binary logic. Ternary logic is a promising alternative to the binary logic design technique thereby attracting a wide community of researchers to contribute in the design of ternary processor. The control unit is effectively the nerve center of a processor that plays a vital role in generating the appropriate control signals and synchronizing all the operations. Design of a control unit is, therefore, the most crucial aspect in processors which have received meager attention in the literature from the ternary perspective. This paper presents design and implementation of an efficient ternary control unit (TCU) for a ternary processor using very-high-speed integrated circuits, and VHSIC hardware description language (VHDL). The functionality of the TCU is verified using sixty-five instructions belonging to various addressing modes. The control signals required for the execution of the instructions are identified and further modeled using VHDL. The paper shows the potential of VHDL modeling and simulation that can be applied to TCU. The extensive simulation results of the designed TCU signify encouraging results that will pave the path for further developments in ternary processors.   Keywords: Multi-valued logic, ternary logic, control unit, VHDLCite this Article Narkhede SS, Chaudhari BS, Kharate GK. Design and implementation of an efficient ternary control unit. Journal of VLSI Design Tools and Technology. 2015; 5(3): 55–70p.
      PubDate: 2015-10-12
      Issue No: Vol. 5 (2015)
  • A High Performance Reference Circuit with Optimized Input Offset
           Operational Amplifier using Device Mismatch Model
    • Authors: Kapil K Rajput, Sanjay Singh, Ravi Saini, Anil K Saini
      Abstract: In this paper, author describes a band gap reference (BGR) circuit, having reference voltage 1.20V with maximum temperature coefficient of 63 ppm/0C in temperature range of –40 to 120  0C. The circuit operates in range of supply voltage, 3.0V to 3.6V. An operational amplifier (op-amp), whose input offset voltage is reduced upto 892 µV using Pelgrom’s device mismatch model is used in BGR. The power supply rejection ratio of circuit is improved at higher frequency and achieved 36 dB at 1 MHz. The circuit having area of 0.45 mm2 in 0.35 µm CMOS technology is designed, fabricated and tested successfully.
      PubDate: 2013-04-15
      Issue No: Vol. 3 (2013)
  • An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based
           Amplifier for Analog Signal-based Applications
    • Authors: Rajinder Tiwari, R K Singh
      Abstract: A low-noise amplifier (LNA), which is based on the cascode feedback methodology, has been commonly used for various wireless protocol-based network applications nowadays. It is so because this topology ensures that the low-noise amplifier (LNA) can achieve quite a high performance and thus, provides a high qualitative output. This amplifier is operated with a low voltage supply in the range of few volts that requires that the impedances of the input and the output to be rather of matched value so as to provide the output with minimum possible noise distortion. Thus, based on this concept/approach, an innovative approach of the design methodology for the design of a CMOS-based low-noise amplifier (CLNA) has been put forward for discussing the performance of the system. Now, in this efficient procedure of the design of CLNA, one has to consider the effective behavior of certain dominant parameters of the circuit such as noise figure, gain, linearity, channel length, etc. The simulation work of the proposed LNA has been carried out with pSpice software using the level 3 parameters based on 0.13 µm CMOS technology that provides the desired outputs. From these experimental results, it has been observed that with the input referred noise of the proposed amplifier 2.5 nV/Hz, the bandwidth of the circuit is in the range of 1 GHz, the power dissipation due to various devices is about 160 μW, with 0.5 dB of low-noise figure and the power consumption in the circuit is as low as 7.0 mW.  
      PubDate: 2012-12-20
      Issue No: Vol. 3 (2012)
  • Power Reduction at 90 nm through Circuit Level Modification
    • Authors: Angshuman Chakraborty, Sambhu Nath Pradhan
      Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns out into degradation of device material, viz., di-electric breakdown, altered component characteristics, etc. This demands additional cooling arrangements to keep the heat density to a minimal operational range. Due to increased power consumption, the battery power also gets drained at a rapid rate. This demands bulky power sources in miniature devices, which is a great hindrance in hand-held portable gadgets. Static power dissipation occurs in run time as well as in active mode of operation of the device. In this work, we have proposed a run time leakage current reduction technique for the CMOS logic circuit at 90 nm technology. As a basic building block, we have selected NAND (universal gate) as our point of focus. We have compared the leakage value of the proposed NAND gate with the leakage of the normal NAND gate. Maximum leakage saving has been obtained more than 90%. The technique is also well suited for the reduction of dynamic power. Simulation results show up to 63.6% in dynamic power saving with small area and delay overhead.
      PubDate: 2012-12-20
      Issue No: Vol. 3 (2012)
  • Low-Voltage Low-Power Single Supply Rail-to-Rail High Resolution
           Comparator in 0.18 µm CMOS Technology
    • Authors: Anil K. Saini, Priyanka Dwivedi, Sanjay Singh
      Abstract: This paper presents an absolute input rail-to-rail ultrahigh-resolution comparator for low-voltage low-power applications. To enhance the input range rail-to-rail, the proposed comparator utilizes dynamic configuration with a MOSFET-only clock booster to supply a boosted voltage for pre-amplifier stage. Cadence SPICE simulations of the proposed comparator in a 0.18 μm CMOS process confirm the rail-to-rail input range with a supply voltage of 1.2 V with a decision time less than 9 ns. The dynamic power consumption of the proposed comparator is 59.3 μW with a clock frequency of 1 MHz.  
      PubDate: 2012-12-20
      Issue No: Vol. 3 (2012)
  • Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High
           Speed Communication System
    • Authors: Anil K. Saini, Sanjay Singh
      Abstract:  In the present work, design of a 10-bit digital-to-analog (D/A) converter using current segmentation architecture in 0.35 µm double-poly, four-metal, CMOS process has been attempted. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.8 and 2.5 least significant bits (LSBs) respectively. For sampling frequency of 12-MSample/s, the spurious free dynamic range (SFDR) is better than 56 dB for signal up to Nyquist rate. The worst case power consumption is 58 mW and it operates with a single supply voltage of 3.3. 
      PubDate: 2012-12-20
      Issue No: Vol. 3 (2012)
  • Detailed Study of Working and Applications of FinFET Technology and Its
           Adaptability in Current Era
    • Authors: Manan Sheth, Shivang Bakliwal, Shival Trivedi, Dhaval Shah
      Abstract:  The CMOS technology is following Moore’s law since almost 25 years. The scaling of CMOS transistor has increased packaging density, speed and decreased power dissipation in the integrated circuits. However, CMOS dimension when scaled to nanometer dimension, many physical barriers arise. In sub-100 nm scale, MOSFET has new variants as SOI implementation and double gate. 
      PubDate: 2012-12-20
      Issue No: Vol. 3 (2012)
  • Performance Analysis of Fe/SiO2/Fe MTJ and Ni/Al2O3/Ni MTJ based
           Magnetoresistive Random Access Memories
    • Authors: Mayank Chakraverty, P. Arun Kumar, Harish M Kittur
      Abstract: This paper reports the first principle simulations of Fe/SiO2/Fe and Ni/Al2O3/Ni magnetic tunnel junctions (MTJs). A performance analysis has been done based upon the device-level simulations of the two magnetic tunnel junctions followed by the circuit level simulations of magnetoresistive random access memory (MRAM) cell operating with the two MTJs respectively. From the device-level simulations, the two MTJs have been compared with regard to the bias dependence of TMR ratios, insulator thickness dependence of TMR ratios and insulator thickness dependence of parallel and anti-parallel state resistances taking the relative magnetizations of the two ferromagnetic films of the MTJs into consideration. From the circuit-level simulations, the static and switching power dissipations have been computed along with the delay time estimation.
      PubDate: 2012-09-10
      Issue No: Vol. 3 (2012)
  • Technology Limits on Differential Gain and Unity-gain Bandwidth of a
           Differential Amplifier: A Theoretical Analysis
    • Authors: Dr. Alpana Agarwal, Dr. Chandra Shekhar
      Abstract: The limiting relationship between differential dc voltage gain and unity-gain bandwidth of an externally unloaded differential amplifier have been explored.  It has been observed that the product of differential dc voltage gain and unity-gain bandwidth of a differential amplifier has an upper limit which is a technology constant.  
      PubDate: 2012-09-10
      Issue No: Vol. 3 (2012)
  • System Level Modeling of ISMB Quadrature Transceiver
    • Authors: Rupam Goswami, Prashant Singh, Narendra Bahadur Singh
      Abstract: In this paper, a new ISMB quadrature transceiver system-level design architecture is presented along with its referenced mathematical models and these were verified using state-of-the-art system modeling tools. Unlike a K-TEK’s receiver, it does not suffer from the timing and template matching problems, and it circumvents processing at high frequencies, thereby reducing the on-chip circuit complexity and power consumption. Hilbert transform has been used at the output of the demodulator for the envelope detection to get the more reliable desired signal that is also the uniqueness in the system. It also presents parallel approach to use a band-pass filter at the output of the demodulator to eliminate the d.c. component to get the desired signal. Matlab coding and Simulink system modeling were parallel done before the design of monolithic integrated circuit using CMOS technology to transfer the similar function on silicon and the objective is completed for most of the blocks. The system-level simulation, presented in this paper, shows the functional behavior of the proposed transceiver. 
      PubDate: 2012-09-10
      Issue No: Vol. 3 (2012)
  • Low Power RF QPSK MODEM Design
    • Authors: Rupam Goswami, Prashant Singh, Narendra Bahadur Singh
      Abstract: System-level simulation including design of CMOS circuits for radio frequency QPSK MODEM targeting applications in 2.45 GHz industrial, scientific and medical (ISM) band has been presented in this paper. Based on the QPSK architecture, the MODEM consists of an analog mixer using a voltage multiplier, a 90 °phase shifter, delay circuits, a voltage adder and a filter to detect the information. A code reuse subsystem block consisting of Chebyshev filter type-II and lowpass RC filters is used prior to determine the envelope of the signal. The design will be useful in analog signal processing for its monolithic integration having higher speed and low cost. The MODEM circuit has been designed using SCL 1.2 µm CMOS foundry’s model parameters. It can operate at a supply voltage of 3.5 V. The circuit consumes power less than 3.5 mW and analog mixer performs a conversion gain of + 9.54 dB (< 10 dB). Simulink system-level simulation verifies the stepwise behavioral aspects of the QPSK architecture and proves that its CMOS circuit’s design presented in the paper shows similarity in the behavior with acceptable performance loss with respect to ideal case. 
      PubDate: 2012-09-09
      Issue No: Vol. 3 (2012)
  • Design of 16-bit Pipelined RISC Processor
    • Authors: Kalyan Acharjya, N. B. Singh
      Abstract: This paper presents the design of efficient and high throughput 16-bit pipelined RISC Processor. The design is challenge with the pipelined stall problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a particular frequency.  The coding is carried out in Verilog HDL and functionality is verified through simulation and test benches at different stages including behavioral and gate level RTL code using Modelsim (Mentor Graphics). The synthesis part is done using Leonardo Spectrum (Mentor Graphics) and implementation done in Xilinx ISE 9.1.  
      PubDate: 2012-09-09
      Issue No: Vol. 3 (2012)
  • Decimator Design for Sigma-Delta ADC
    • Authors: Tripti Sharma, Prashant Singh, Narendra Bahadur Singh
      Abstract: This paper describes the design of a decimator which is used in digital signal processing as well as 10-bit sigma-delta analog-to-digital converter to down sample the incoming signal for further applications. It is also used for verification of the sigma-delta modulator functionality to reconstruct the incoming signal. The design has been carried out using 180 nm TSMC, CMOS foundry parameters for spice level 49 model parameters in TANNER EDA (Tspice). The results for the presented decimator model are mentioned in the paper; the higher decimation factor can be taken similarly as per requirement.
      PubDate: 2012-05-11
      Issue No: Vol. 3 (2012)
  • Design of CMOS AM Modem for Wireless Sensors
    • Authors: Shipra Suman, Narendra Bahadur Singh
      Abstract: A design of amplitude modulated (AM) modem, compatible to CMOS technology for its monolithic integration with either wireless microsensors or other sources of baseband signals, is presented in this paper operating in different frequency bands. Circuits functional in different operating conditions are considered in the paper to satisfy the requirement from low- to high-speed signals produced either from the wireless sensor or other signal source to be modulated on a MHz or GHz carrier signal in the industrial scientific and medical (ISM) band. Different modem circuit designs are presented in the paper right from the module up to the schematic level after their analysis, circuit simulations are carried out using spice with its equivalent Hspice MOS model level 13 for the CMOS process of SCL 1.2 micrometer semiconductor foundry.
      PubDate: 2012-05-11
      Issue No: Vol. 3 (2012)
  • An FPGA-based Controller Design for Servo Actuator Using Xilinx System
           Generator and HDL Cosimulator
    • Authors: thangavel ananthan, M. V. Vaidyan, M. V. Varghese
      PubDate: 2012-05-11
      Issue No: Vol. 3 (2012)
  • High-speed CMOS ADCs Design
    • Authors: Prashant Singh, Narendra Bahadur Singh
      Abstract: This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. Its simulation studies with design iterations were carried out using EDA tools. Pre- and post-layout electrical behavior verification of the circuit was carried out for the circuits from its layout as well as netlist extracted circuit from its schematic. Best performance has been achieved by the design iterations as presented in the paper.
      PubDate: 2012-05-11
      Issue No: Vol. 3 (2012)
  • Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort
           and Transistor Sizing
    • Authors: Sampath Kumar V., neerja Singh
      Abstract:  With logical effort minimum delay of the path can be estimated by only knowing number of stages, path effort, and parasitic delay without the need to assign transistor sizes. This is superior to simulation where delay depends on sizes and you never achieve certainty that the size selected would offer minimum delay. In this work 3 cascaded inverters is being sized in the ratio 1:2:3 to achieve minimum propagation delay and comparison is made with the 3 cascaded inverter not sized in the ratio 1:2:3. 
      PubDate: 2012-05-11
      Issue No: Vol. 3 (2012)
  • Gain Controlled Sinusoidal Oscillator Using Current Controlled Current
    • Authors: Mourina Ghosh, Subhajit Bhattacharya, Ashish Ranjam, Sajal K. Paul
      Abstract: A gain-controlled sinusoidal oscillator circuit based on current-controlled current conveyors (CCCII) is introduced. The circuit contains three CCCIIs and two grounded capacitors and no resistor. The amplitude of the output current can be controlled electronically. Hence, the proposed topology is suitable for IC implementation. The CCCII has been implemented using 0.35 µm CMOS technology and the PSPICE simulation results are given.
      PubDate: 2012-02-06
      Issue No: Vol. 3 (2012)
  • Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network
           at 0.18 µm Technology
    • Authors: Abhishek Sharma
      Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze the rise time and settling time in similar analysis. The model evaluates the performance of a system which is expressed in terms of the transient response for the unit impulse input because it is easy to generate and evaluate the delay analytically. The transient response of a system to a unit impulse input depends upon the initial conditions. In this paper, a new interconnect model is presented; the model is based on the RLCG transmission line whose response is evaluated in time domain for a unit impulse input. In this model the delay is calculated in SPICE and MATLAB. No approximation is made to the transfer function of the interconnect. A closed form expression for the propagation delay of a CMOS gate driving a distributed RLCG line is introduced. On-chip inductance and conductance are shown to have a profound effect on the high performance IC design methodologies. In this proposed model we have shown that with the increase in the value of conductance by keeping constant the values of R, L, C we evaluate that the SPICE delay reduces but if we compare it with the MATLAB proposed delay model we see very accurately that the variation in the proposed delay is much larger in comparison to the SPICE delay. Hence, for a high-speed circuit, one must increase the value of G, so that the steady-state condition is reached as soon as possible. The simulation results performed in Cadence SPICE environment justify the efficiency of the proposed model.
      PubDate: 2012-02-06
      Issue No: Vol. 3 (2012)
  • An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC
           Interconnect Modeled with Skin Effect with Step and Ramp Input
    • Authors: Shilpi Lavania, Sunil Kumar Sharma
      Abstract: As the technology is acquiring frequency of the Giga-hertz range noise and delay calculations and avoidance of such factors in VLSI interconnects have become dominant to be considered. This paper represents a comparison between the crosstalk noise voltage level measured when the RLC on-chip interconnect was modeled when the skin effect was considered under step input and the crosstalk voltage measured when the RLC line was modeled with skin effect under ramp input. In this paper, we have proposed a detailed discussion about the relevance of the input applied to any interconnect that can affect the whole system integrity. The importance and dominance of the skin effect cannot be ignored. But apart from the high frequency effect like skin effect and proximity effect, it is also very important to observe that these factors may harm the system integrity if the wrong input is applied. This paper reflects the approximated noise and delay variations in different cases of inputs applied to the Global RLC interconnect. 
      PubDate: 2012-02-06
      Issue No: Vol. 3 (2012)
  • Analysis of Resource Utilization for a Floating-Point Complex
           Multiplication in FPGA
    • Authors: Anitha Mary, Dojin Domnic, Dr. K. Rajasekaran
      PubDate: 2011-07-22
      Issue No: Vol. 3 (2011)
  • Power Estimation for VLSI Circuits Using Neural Networks
    • Authors: Srinath B.
      PubDate: 2011-07-22
      Issue No: Vol. 3 (2011)
  • Analysis of VLSI Circuits Designed with Single and Dual Channel Strained
           Silicon MOSFETs in Nanoregime
    • Authors: Neha Sharan, Ashwani Rana
      PubDate: 2011-07-22
      Issue No: Vol. 3 (2011)
  • Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect
    • Authors: Vikas Maheshwari, Shilpi Lavania, Dr. Rajib Kar, Dr. Durbadal Mandal, Dr. A. K. Bhattacharjee
      PubDate: 2011-07-22
      Issue No: Vol. 3 (2011)
  • Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance
           Current Conveyors
    • Authors: Ashutosh Tripathi
      PubDate: 2011-07-22
      Issue No: Vol. 3 (2011)
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